Bitline contact (BLC), bitline (BL), and node contact (NC) fabrication are three interacting process loops during DRAM fabrication. BLC characteristics play an important role in subsequent BL and NC process loops. The complex structure of DRAM increases the difficulty of identifying the impact of BLC process variations on device shorts (BVC test failures) and device opens (DVC test failures). In this work, virtual DOEs using SEMulator3D® (Lam Research’s virtual fabrication platform) were carried out to better understand the effect of BLC characteristics on DVC and BVC failures, including BLC X and Y axis CD, etch sidewall angles, overlay (OVL) shift and roughness. From our studies, we have developed optimized process specification for X and Y axis CD, etch sidewall angles, OVL shift, and roughness during the bitline contact process loop. The results of this type of experiment can help developers identify key specifications and save resources during the early design phase of DRAM process development.
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