Electrical architecture and development of the digital processing unit of the payload onboard the LiteBIRD space mission

D. Rambaud; S. Maestre; B. Mot; L. Montier

doi:10.1117/12.3019696

23 August 2024 Electrical architecture and development of the digital processing unit of the payload onboard the LiteBIRD space mission

D. Rambaud, S. Maestre, B. Mot, L. Montier

Author Affiliations +

Proceedings Volume 13092, Space Telescopes and Instrumentation 2024: Optical, Infrared, and Millimeter Wave; 1309272 (2024) https://doi.org/10.1117/12.3019696
Event: SPIE Astronomical Telescopes + Instrumentation, 2024, Yokohama, Japan

Conference Poster

Abstract

LiteBIRD is a JAXA strategic L-Class mission whose objective is the study of B-mode polarization from the cosmic background (CMB) radiation detection. Observations need to be conducted over a wide frequency range (34 GHz – 448 GHz) by three telescopes (the Low, Middle and High-Frequency Telescopes). We describe the electrical architecture of these instruments and the architecture of the Instrument Control Unit (ICU) of the payload. The ICU is composed of a new SRAM based FPGA component NG-ULTRA (4 x R52 ARM processor + FPGA on a chip) from the French manufacturer NanoXplore. We present more particularly the science data streams, the science on-board processing pipeline and the use of an embedded space-qualified payload generic software from CNES on the top of an hypervisor called XNG.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

D. Rambaud, S. Maestre, B. Mot, and L. Montier "Electrical architecture and development of the digital processing unit of the payload onboard the LiteBIRD space mission", Proc. SPIE 13092, Space Telescopes and Instrumentation 2024: Optical, Infrared, and Millimeter Wave, 1309272 (23 August 2024); https://doi.org/10.1117/12.3019696

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