Paper
26 August 2024 Nanoimprint performance improvements for high volume semiconductor device manufacturing
Shinichi Shudo, Hirotoshi Torii, Yoshio Suzaki, Atsushi Kimura, Kiyohito Yamamoto, Mitsuru Hiura, Keita Sakai, Yukio Takabayashi
Author Affiliations +
Abstract
Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint Lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. To establish a new lithographic production solution requires the support of an system in order to enable seamless insertion of the technology. In this paper, review the current NIL tool performance regarding overlay, defectivity and throughput. And we also touch on other applications that can be addressed with NIL.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Shinichi Shudo, Hirotoshi Torii, Yoshio Suzaki, Atsushi Kimura, Kiyohito Yamamoto, Mitsuru Hiura, Keita Sakai, and Yukio Takabayashi "Nanoimprint performance improvements for high volume semiconductor device manufacturing", Proc. SPIE 13177, Photomask Japan 2024: XXX Symposium on Photomask and Next-Generation Lithography Mask Technology, 1317708 (26 August 2024); https://doi.org/10.1117/12.3034104
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KEYWORDS
Overlay metrology

Optical lithography

Semiconducting wafers

Molybdenum

Manufacturing

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