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26 August 2024 Improvement of mask pattern placement error using novel resist charging control methodology in multi-beam mask writer
Hyoyeon Kim, Hyungrae Noh, Wonsik Shin, Kangho Park, Youngjae Lee, Sangho Jo, Youngsu Sung, Hojune Lee, Heebom Kim, Jin Choi, Sanghee Lee, Alexander Egl, Gottfried Hochleitner, Matthias Kühmayer, Matthias Liertzer, Francesco Massa, Mathias Tomandl
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Proceedings Volume 13177, Photomask Japan 2024: XXX Symposium on Photomask and Next-Generation Lithography Mask Technology; 131770V (2024) https://doi.org/10.1117/12.3032199
Event: Photomask Japan 2024, 2024, Yokohama, Japan
Abstract
As wafer manufacturing shrinks size and pitch of features, and EUV lithography introduces high NA, the control of photomask pattern placement error that contributes to wafer overlay becomes a critical requirement for leading-edge devices. For sub-3nm node devices, the pattern complexity has increased and the exposure dose has also risen due to the use of low-sensitivity resist. Accordingly, to improve the pattern fidelity and reduce the exposure time, masks are manufactured using Multi-Beam Mask Writer (MBMW). As a result of analyzing the mask pattern placement error budget for the main EUV resist of sub-3nm node device, e-beam resist charging was found to be the most significant factor. This is primarily due to the inability to use a charging dissipation layer (CDL), caused by defect issues and degradation of critical dimension (CD) linearity. In this paper, we conduct an in-depth analysis of mask pattern placement errors induced by the charging effect in the MBMW and present a charging control methodology to mitigate these pattern-density-dependent errors. We test the charging effect reduction, an integrated solution of hardware and software for charging control in the MBMW, and showcase its performance for two resists. When applied to mass productions, the charging effect correction (CEC) significantly reduces mask pattern placement errors in a single cell and improves mask overlay between two critical layers aligned in an overlay alignment scheme. Ultimately, this leads to a reduction of wafer in-field overlay error.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
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Hyoyeon Kim, Hyungrae Noh, Wonsik Shin, Kangho Park, Youngjae Lee, Sangho Jo, Youngsu Sung, Hojune Lee, Heebom Kim, Jin Choi, Sanghee Lee, Alexander Egl, Gottfried Hochleitner, Matthias Kühmayer, Matthias Liertzer, Francesco Massa, and Mathias Tomandl "Improvement of mask pattern placement error using novel resist charging control methodology in multi-beam mask writer", Proc. SPIE 13177, Photomask Japan 2024: XXX Symposium on Photomask and Next-Generation Lithography Mask Technology, 131770V (26 August 2024); https://doi.org/10.1117/12.3032199
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KEYWORDS
Error analysis
Semiconducting wafers
Calibration
Logic
Overlay metrology
Logic devices
Image registration
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