Architecture and performance of a hardware collision-checking accelerator

R. Keith Bardin; Vibeke Libby

doi:10.1117/12.49850

1 December 1991 Architecture and performance of a hardware collision-checking accelerator

R. Keith Bardin, Vibeke Libby

Proceedings Volume 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II; (1991) https://doi.org/10.1117/12.49850
Event: San Diego, '91, 1991, San Diego, CA, United States

Abstract

As is well know, collision checking in a generalized sense is a substantial contributor to processor load in a wide range of path-planning applications. These include high-speed terrain following and obstacle avoidance in low-flying aircraft, path planning on local scales for autonomous vehicles, both undersea and on land, and a number of areas in robotic motion planning, not only for mobile robot navigation but also for such problems as arm motion in cluttered environments. Some algorithms have been quoted as requiring from 80% to as much as 95% of the available path-planning time for collision checking. Under such conditions, special-purpose hardware designed for the requirements of collision checking offers the promise of major overall performance improvements in real-time path planning. Recent work at the Lockheed Palo Alto Research Laboratories has produced a hardware system providing a major acceleration in collision-checking capability with minimal added hardware, and demonstrated an approach leading to still further major increments in speed for this function. This paper first describes the architecture of the system, which is known as TIGER (Three- dimensional Intersect & Geometrical Evaluator in Real time). This is followed by an analysis of the computational load of the collision-checking problem and a discussion of important design and performance considerations arising from the approach both within TIGER itself and in the integration of TIGER into a higher-level path-planning system.

Citation Download Citation

R. Keith Bardin and Vibeke Libby "Architecture and performance of a hardware collision-checking accelerator", Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); https://doi.org/10.1117/12.49850

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