Integrated circuit critical-dimension optimization through correlation of resist spin speed, substrate reflectance, and scanning electron microscope measurements

Anne M. Kaiser; Robert M. Haney

doi:10.1117/12.59802

1 June 1992 Integrated circuit critical-dimension optimization through correlation of resist spin speed, substrate reflectance, and scanning electron microscope measurements

Anne M. Kaiser, Robert M. Haney

Author Affiliations +

Proceedings Volume 1673, Integrated Circuit Metrology, Inspection, and Process Control VI; (1992) https://doi.org/10.1117/12.59802
Event: Microlithography '92, 1992, San Jose, CA, United States

Abstract

A procedure is described for predicting the optimum resist thickness to insure a reflectivity minimum at the wavelength of interest regardless of the underlying surface reflectivity. An experiment was performed using polysilicon on oxide wafers to demonstrate that uniform CDs could be patterned for a variety of reflectances.

Citation Download Citation

Anne M. Kaiser and Robert M. Haney "Integrated circuit critical-dimension optimization through correlation of resist spin speed, substrate reflectance, and scanning electron microscope measurements", Proc. SPIE 1673, Integrated Circuit Metrology, Inspection, and Process Control VI, (1 June 1992); https://doi.org/10.1117/12.59802

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