CCD operation using the high-speed imager test station

Kevin L. Albright; George J. Yates; Nicholas S. P. King; Thomas E. McDonald Jr.; Bojan T. Turko

doi:10.1117/12.145796

1 January 1993 CCD operation using the high-speed imager test station

Kevin L. Albright, George J. Yates, Nicholas S. P. King, Thomas E. McDonald Jr., Bojan T. Turko

Proceedings Volume 1801, 20th International Congress on High Speed Photography and Photonics; (1993) https://doi.org/10.1117/12.145796
Event: 20th International Congress on High Speed Photography and Photonics, 1992, Victoria, BC, Canada

Abstract

The use of a high-speed (up to 100 MHz) programmable pattern generator and special clock driver/translator circuits for clocking solid-state multiple output imagers is discussed. A specific example of clocking a developmental 256 X 512 two-port CCD is illustrated. Reference to a prior report of clocking an eight-port CCD is included. Future use in clocking a CID imager is discussed.

Citation Download Citation

Kevin L. Albright, George J. Yates, Nicholas S. P. King, Thomas E. McDonald Jr., and Bojan T. Turko "CCD operation using the high-speed imager test station", Proc. SPIE 1801, 20th International Congress on High Speed Photography and Photonics, (1 January 1993); https://doi.org/10.1117/12.145796

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