Malleable architecture generator for FPGA computing

Maya Gokhale; James Kaba; Aaron Marks; Jang Kim

doi:10.1117/12.255818

21 October 1996 Malleable architecture generator for FPGA computing

Maya Gokhale, James Kaba, Aaron Marks, Jang Kim

Proceedings Volume 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic; (1996) https://doi.org/10.1117/12.255818
Event: Photonics East '96, 1996, Boston, MA, United States

Abstract

The malleable architecture generator (MARGE) is a tool set that translates high-level parallel C to configuration bit streams for field-programmable logic based computing systems. MARGE creates an application-specific instruction set and generates the custom hardware components required to perform exactly those computations specified by the C program. In contrast to traditional fixed-instruction processors, MARGE's dynamic instruction set creation provides for efficient use of hardware resources. MARGE processes intermediate code in which each operation is annotated by the bit lengths of the operands. Each basic block (sequence of straight line code) is mapped into a single custom instruction which contains all the operations and logic inherent in the block. A synthesis phase maps the operations comprising the instructions into register transfer level structural components and control logic which have been optimized to exploit functional parallelism and function unit reuse. As a final stage, commercial technology-specific tools are used to generate configuration bit streams for the desired target hardware. Technology- specific pre-placed, pre-routed macro blocks are utilized to implement as much of the hardware as possible. MARGE currently supports the Xilinx-based Splash-2 reconfigurable accelerator and National Semiconductor's CLAy-based parallel accelerator, MAPA. The MARGE approach has been demonstrated on systolic applications such as DNA sequence comparison.

Citation Download Citation

Maya Gokhale, James Kaba, Aaron Marks, and Jang Kim "Malleable architecture generator for FPGA computing", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255818

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