Digital Pipelined Hardware Median Filter Design For Real-Time Image Processing

Dennis J. Delman

doi:10.1117/12.932528

30 July 1982 Digital Pipelined Hardware Median Filter Design For Real-Time Image Processing

Dennis J. Delman

Author Affiliations +

Proceedings Volume 0298, Real-Time Signal Processing IV; (1982) https://doi.org/10.1117/12.932528
Event: 25th Annual Technical Symposium, 1981, San Diego, United States

Abstract

A hardware median filter is described which is designed to filter imagery at a real-time rate of 10X106 pixels/second. The data is windowed with line buffers, and propagates through n pipe lined stages where n is the number of bits in a pixel. The algorithm described is a form of the radix method of Atamanl modified to reduce the decisionmaking at each stage. Each stage is nearly identical thus making the filter very structured and modular. The filter can be implemented with available logic components and would be useful as a preprocessor in a pattern recognition system.

Citation Download Citation

Dennis J. Delman "Digital Pipelined Hardware Median Filter Design For Real-Time Image Processing", Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); https://doi.org/10.1117/12.932528

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