Process optimization of dual-gate CMOS

I. Min Liu; Yuh Yue Chen; Chris Connor; Atul B. Joshi; Dim-Lee Kwong

doi:10.1117/12.284621

27 August 1997 Process optimization of dual-gate CMOS

I. Min Liu, Yuh Yue Chen, Chris Connor, Atul B. Joshi, Dim-Lee Kwong

Author Affiliations +

Proceedings Volume 3212, Microelectronic Device Technology; (1997) https://doi.org/10.1117/12.284621
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

In this paper, we study and compare dual-gate CMOS devices fabricated with various processes such as standard or NO- nitrided gate oxides, polycrystalline or amorphous silicon gates, boron or BF₂ implantation for p⁺-poly and S/D formation, and different drive-in conditions. It is found that NO nitridation of gate oxides can improve device performance for short channel PMOSFETs over control SiO₂. However, pile-up of boron in nitrided gate oxides may degrade gate oxide reliability in PMOS devices. Amorphous silicon gates can effectively prevent boron penetration into gate oxides at a cost of aggravated poly-depletion effects. When BF₂ implantation is used for p⁺-poly formation, fluorine improves the resistance of SiO₂/Si interfaces to hot-carrier stress but it enhances boron diffusion in gate oxides. The process optimization of dual-gate CMOS regarding device performance and hot-carrier reliability is systematically studied.

Citation Download Citation

I. Min Liu, Yuh Yue Chen, Chris Connor, Atul B. Joshi, and Dim-Lee Kwong "Process optimization of dual-gate CMOS", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284621

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