Novel Multibit Convolver/Correlator Chip Design Based On Systolic Array Principles

J. G. McWhirter; J. V. McCanny; K. W. Wood

doi:10.1117/12.933697

28 December 1982 Novel Multibit Convolver/Correlator Chip Design Based On Systolic Array Principles

J. G. McWhirter, J. V. McCanny, K. W. Wood

Author Affiliations +

Proceedings Volume 0341, Real-Time Signal Processing V; (1982) https://doi.org/10.1117/12.933697
Event: 1982 Technical Symposium East, 1982, Arlington, United States

Abstract

A novel multi-bit convolver/correlator circuit is described. The circuit has been designed to operate as a systolic array of simple one bit processor and memory cells and, as a result it can operate at relatively high data rates by making efficient use of silicon area. Since the design is extremely regular in nature and requires very little control it should be easy to implement in VLSI technology. The size of circuit which can be fabri-cated and the data rate which can be achieved will of course depend on the specific tech-nology which is chosen.

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J. G. McWhirter, J. V. McCanny, and K. W. Wood "Novel Multibit Convolver/Correlator Chip Design Based On Systolic Array Principles", Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); https://doi.org/10.1117/12.933697

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