Formal specification and verification of hardware designs

S. Ramesh; S.S.S.P Rao; G. Sivakumar; Purandar Bhaduri

doi:10.1117/12.328817

1 September 1998 Formal specification and verification of hardware designs

S. Ramesh, S.S.S.P Rao, G. Sivakumar, Purandar Bhaduri

Proceedings Volume 3412, Photomask and X-Ray Mask Technology V; (1998) https://doi.org/10.1117/12.328817
Event: Photomask Japan '98 Symposium on Photomask and X-Ray Mask Technology V, 1998, Kawasaki City, Japan

Abstract

Designing modern processors is a great challenges as they involve millions of components. Traditional techniques of testing and simulation do not suffice as the amount of testing required is quite enormous. Design verification is an effective alternative technique for increasing the confidence in the design. Formal verification involves checking whether the system being verified behaves as per the specification using mathematical techniques. In this paper we describe some techniques for enhancing the use of formal methods for the specification and verification of hardware system. We examine how the language Esterel can be used to specify and verify properties of pipelined microprocessor. We also discuss methods for taking hardware descriptions of simple circuits written in VHDL and automatically generating the inputs needed by a theorem prover to prove properties of the circuit.

Citation Download Citation

S. Ramesh, S.S.S.P Rao, G. Sivakumar, and Purandar Bhaduri "Formal specification and verification of hardware designs", Proc. SPIE 3412, Photomask and X-Ray Mask Technology V, (1 September 1998); https://doi.org/10.1117/12.328817

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