Paper
2 June 2000 Lithography process control and optimization based on defect capture and reduction
Jeffrey A. Leavey, John Boyle, Andrew Skumanich
Author Affiliations +
Abstract
Defect monitoring is increasingly required for advanced line maintenance. A critical decision is how to proceed with lot deposition if an excursion is detected. A methodology based on defect inspection and defective die count analysis was employed which provided effective process monitoring and yield maintenance. The methodology allows rapid decision-making with a minimum of information for lot disposition. The purpose is to separate significant excursions from temporary fluctuations in order to appropriately focus defect reduction resources. Wafers are systematically inspected post-litho with a patterned wafer inspection system, the WF736, and the number of die with killer defects is counted and then monitored with time. Every lot is inspected, full wafer inspection is performed, and all defect types are captured. By determining the killer defect progression after re-work, it is possible to establish lot disposition. If the count is still high, defect reduction analysis is then applied. Various defects were flagged and addressed, arising both from litho and from prior steps. In addition, the wafer inspection was utilized for dose forecasting with a feed-forward to appropriately modify the optimal dose. Good line control and yield maintenance were observed.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jeffrey A. Leavey, John Boyle, and Andrew Skumanich "Lithography process control and optimization based on defect capture and reduction", Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); https://doi.org/10.1117/12.386484
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Cited by 1 scholarly publication.
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KEYWORDS
Inspection

Wafer inspection

Process control

Defect inspection

Lithography

Semiconducting wafers

Etching

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