Application of a dynamically reconfigurable cell-array processor to an MPEG-2 video decoder

Kiyotaka Komoku; Fumihiro Hatano; Takayuki Morishita; Iwao Teramoto

doi:10.1117/12.402526

6 October 2000 Application of a dynamically reconfigurable cell-array processor to an MPEG-2 video decoder

Kiyotaka Komoku, Fumihiro Hatano, Takayuki Morishita, Iwao Teramoto

Proceedings Volume 4212, Reconfigurable Technology: FPGAs for Computing and Applications II; (2000) https://doi.org/10.1117/12.402526
Event: Information Technologies 2000, 2000, Boston, MA, United States

Abstract

We have proposed and developed the Dynamically Reconfigurable Cell-Array Processor (DRCAP) that consists of functional Cell Arrays (CAs), and buses/bus-switches that provide with connections between CAs. A software simulator of the DRCAP is constructed, on which the MPEG-2 video decoder is successfully implemented. This MPEG-2 decoder dynamically changes the configuration in many times during the decoding process. The processing is executed every macro-block, reconfiguring in each component process of the MPEG-2 decoding such as the variable length decoding, the dequantization, the inverse DCT, and so on. The resources required for the DRCAP to decode the MPEG-2 MP@ML video stream is investigated. In the simulation it is found that the numbers of CAs to decode the MPEG-2 MP@ML video stream are 8 for PCAs, 1 for LCA, 2 for CCAs and 35 for MCAs, and the execution cycle required is 94.6MHz. In the case of doubling all configurations, where the same two processes are executed in parallel, the numbers of CAs are 15, 1, 4 and 69, for PCA, LCA, CCA and MCA, respectively, and the execution frequency of 55.9MHz is required.

Citation Download Citation

Kiyotaka Komoku, Fumihiro Hatano, Takayuki Morishita, and Iwao Teramoto "Application of a dynamically reconfigurable cell-array processor to an MPEG-2 video decoder", Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); https://doi.org/10.1117/12.402526

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