Experience With The CMU Programmable Systolic Chip

Allan L. Fisher; H. T. Kung; Kenneth Sarocky

doi:10.1117/12.944017

28 November 1984 Experience With The CMU Programmable Systolic Chip

Allan L. Fisher, H. T. Kung, Kenneth Sarocky

Author Affiliations +

Proceedings Volume 0495, Real-Time Signal Processing VII; (1984) https://doi.org/10.1117/12.944017
Event: 28th Annual Technical Symposium, 1984, San Diego, United States

Abstract

The CMU programmable systolic chip (PSC) is an experimental, microprogrammable chip designed for the efficient implementation of a variety of systolic arrays. The PSC has been designed, fabricated, and tested. The chip has about 25,000 transistors, uses 74 pins, and was fabricated through MOSIS, the DARPA silicon broker, using a 4 micron nMOS process. A modest demonstration system involving nine PSCs is currently running. Larger demonstrations are ready to be brought up when additional working chips are acquired. The development of the PSC, from initial concept to a silicon layout, took slightly less than a year, out testing, fabrication, and system demonstration took an additional year. This paper reviews the PSC, describes the PSC demonstration system, and discusses some of the lessons learned from the PSC project.

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Allan L. Fisher, H. T. Kung, and Kenneth Sarocky "Experience With The CMU Programmable Systolic Chip", Proc. SPIE 0495, Real-Time Signal Processing VII, (28 November 1984); https://doi.org/10.1117/12.944017

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