On the occasion of 10th conference of Photomask Japan, the advancement of this conference in the past decade is briefly reviewed and some emerging technologies related to lithography are discussed with examples.

A new att-PSM shifter for both F₂ and high-transmittance ArF lithography was developed. This shifter consists of SiON / TaHf in stacked layers. SiON for phase shift layer has a moderate transmittance and refractive index, and has sufficient laser durability. The TaHf film, which is a transmittance control layer, was effective as a functional layer in mask dry etching. Adopting the 3 step etching procedure, low damage of the quartz surface and less impact to CD shift was realized. It was confirmed that a new shifter has also sufficient feasibility to the mask inspection and repair process.

A method based on UV in air environment to improve the stability of the material of the photoreticles throughout cleans repeated over is suggested in this work. A typical aggressive clean was performed on two different Embedded Shifter materials, 193nm Molybdenum-Silicon-Oxy-Nitride (MoSiON) and 193nm Multilayer Silicon Nitride-Titanium Nitride (SiN-TiN). The variation of phase and transmission of each reticle is reported with the number of cleans. Given the appropriate exposure the phase and the transmission of the treated materials were significantly improved. All treated EAPSMs could stand cleans repeated over.

The mask fabrication industry is slowly migrating to chemically amplified (CA) resists to take the advantages of their high contrast, resolution, and sensitivity. During this migration process, the industry has encountered several problems associated with CA resists such as baking homogeneity of thick mask plates on hot plates, footing on Cr masks, and storage stability of mask blanks. In addressing these issues, we have adopted a low Ea CA resist platform to overcome the bake latitude issue. The resist formulation has been reformulated to reduce the footing and a new package method has been introduced to extend the storage of the blanks. In addition, we will also discuss our studies on two major areas, such as sensitivity and etch resistance, which we think is extremely important for E-beam resists in the future. The mask industry started with 248nm DUV CA resist systems and then found out that there was a need for even higher sensitivity resist systems to address the throughput issue. In our early study, we have observed that by simply increasing photoacid generator loading in the resist formulation we were able to increase the sensitivity, but there was a significant reduction in the dose latitude. After studying the dissolution and inhibition properties of different PAGs, we have been able to optimize PAG and base loading in combination with proper choice of PAGs to achieve high sensitivity and large dose latitude. The new resist formulation exhibits a large dose latitude of 38% for 100 nm l/s images with high sensitivity of 4.4μC/cm² at 100 kV. Due to the electron scattering effect and the image collapse issues with thicker resists, thinner imaging layer is desirable. Sufficient etch selectivity is needed to compensate the insufficient resist thickness. Therefore, there is a need to develop a high Cl₂/O₂ RIE (used in Cr etch process) etch resistant resist system for mask making. We have reported earlier that a resist formulation based on blending KRS-XE with SSQ polymer has resolved 50nm l/s resist images with etch rate 20% better than conventional novolak I-line resist systems. Since then, we have investigated a few new SSQ polymers and found some lithographic improvement in this new blending systems due to better compatibility of the SSQ polymer to the KRS-XE.

In recent years, more precise pattern dimension control (CD control) on a photomask has been required than ever as finer-line of IC pattern progresses. In the case of the conventional development (spray-development, puddle-development), CD control is difficult due to loading and micro-loading effect. The "loading and micro-loading effect" refers to the differences of exposed area around the pattern. The low pattern density generates numerous dissolution products and decreases the concentration of developer. This phenomenon changes resist dissolution rate and causes difficulties in controlling the CD. To solve this problem, we have been developing a new type of developer, called "Proximity Gap Suction Development (PGSD)." Nozzle of PGSD has five slits; opening for supplying developer is in the center, two suction slits are on the both sides, and two slits for rinse are on the very end. The proximity gap is kept between the nozzle surface and resist during development. Contaminated developer is immediately sucked/removed and stable development can be achieved by the continuous dispense of fresh developer at high speed. Thus, a desired pattern size can be obtained without loading and micro loading effect. We reported the principle of PGSD at BACUS in 2002. In this thesis, we would like to report the following topics. (1) System overview of α machine, which we are currently developing. (2) Effect of the PGSD on CD uniformity and the number of defects.

As critical dimensions (CDs) continue to approach the 90 nm node, it is inevitable that the industry has employed the use of chemically amplified resist (CAR) with 50 kV e-beam writing tool. However, the fogging effect by re-scattered incident electron at a high acceleration e-beam writer and the loading effect at dry etching step due to pattern density are critical issues since these effects make the variation of CD mean to target (MTT) and the degradation of CD uniformity. Tracking the CD error sources in CD uniformity and minimizing the error are very important task for high technology node mask production. In this paper, we focus on finding the source of the radial error in CD uniformity for each process step since the radial error occupy the main part of total CD uniformity. Also we present the radial error modeling using convolution equation between Gaussian CD error distributions with pattern densities. Finally, we describe the radial error correction method by phantom exposure with rectangle representing local pattern density. Fogging effect at writing process is one of the main sources of the radial error in global CD uniformity. The error by fogging effect is linearly proportional to mask pattern density, whereas loading effect at dry etch process increases the radial error in the case of the higher pattern density. The correction method using defocused beam based on our CD uniformity model effectively reduces the radial error and total error to 50% of their original value.

Microloading in photomask fabrication is a key parameter in process optimization. A Variable Bias Model has been successfully used in explaining etch proximity behavior during wafer etching. This model recently became part of the VT5 model suit. In this study, we apply variable bias modeling to the dry etching in mask fabrication. A special etch test pattern is used to characterize etch bias under various process conditions. We show that etch proximity is adequately described by two proximity parameters: density and separation. The model coefficients depend on the process parameters and can be used to characterize and explain etch behavior in terms of microloading and etch aperture effects. Ability to explain mask etching is important for accurate OPC modeling. While some modeling methodologies consider mask and wafer processes as a single "black box," we found that more accurate OPC models are generated by building separate models for mask-making, optical, and wafer processing steps. We show how variable etch model can be used to compensate for iso-dense mask bias and how this step fits into OPC flow.

Chamber surface condition in high-density plasma etch reactors can dramatically affect process performance. The well-known “first wafer effect” in wafer etch processes is often reduced by a “seasoning” process which runs an appropriate etch chemistry on a dummy wafer prior to the etch of a production wafer. The seasoning process has proven to be an effective method for minimizing wafer process shift, but it has not been examined for photomask production using typical dry etch chemistries. In this work, a series of PR/Cr/Quartz photomasks were etched in a Etec Systems, Inc. Tetra photomask etch system with the goal of quantifying the amount of change in etch rate and critical dimension (CD's) following an isopropanol “wet” cleaning of the chamber, as well as the amount of seasoning necessary to minimize the observed process shift using a standard Cl₂/O₂/He chemistry. The chamber seasoning and etch processes were observed via in-situ recording of optical emission from the plasma reactor with a CCD array and monochromator. Alumina coupons affixed to different areas of the chamber prior to mask seasoning/etching were subjected to X-Ray Photoelectron Spectroscopy as well as Time of Flight Secondary Ion Mass Spectrometry (TOF-SIMS) to determine the identity of the chemical species deposited in the chamber during the seasoning/etching process. Results from these etching processes clearly indicated the presence of a “first mask effect,” which can be reduced by a seasoning process appropriate for the particular chemistry involved. Alumina coupon surface analysis revealed a negligible amount of deposition accumulating during the experiments.

As the design rule of lithography becomes smaller, printability of reticle defect to wafer is critical for the photomask manufacturing technology. In order to improve the controllability of reticle defects, inspection and repair systems are expanding their capability by continuously modifying hardware and software. This is a good solution to detect and review the defect but it is indirect approaching to reduce the defect in the photomask process. To produce the photomask of defect free or low defect density, effort is needed to improve the capability of defect control in the mask-making process and to evaluate the source of hard defect as well as soft defect. In this paper, we concern the defect source and the feature of printed defects in photomask manufacturing steps. We also discuss the efforts to eliminate the defect source and to control the mask-making process with low defect density. In order to eliminate the source of defects, we partition the mask-making process with defect inspection system, SLF27 TeraStar and Lasertec MD2000, and review a defect shape with CD SEM and AFM. And we compare printed defects, which exist in each process steps, after dry etching process.

Inspection of aggressive OPC represents one of the major challenges for today's mask inspection methodologies. Systems are phased with high-density layouts, containing OPC features far below the resolution limit of conventional inspection systems. This causes large amounts of false and nuisance defects, especially on production applications. The paper presents the use of Aera193, a new inspection system using aerial imaging as inspection methodology.

The implementation of low k₁ 193nm lithography for 90nm node IC production brings new challenges to reticle inspection systems. The inspection tools have to deal with new attenuating films, smaller and more complex features, and more aggressive OPC. In addition, low k₁ lithography causes the mask error factor (MEEF) to increase, magnifying CD errors. This, in turn, makes reticle defect detection specifications more aggressive. Achieving high sensitivity, low false defect count, for a full plate inspection is a big challenge. Those three (high sensitivity, low false defect count, full plate inspection) are the three “legs” that must support real die-to-database inspection. In order to demonstrate inspection success, all three must be achieved. Without any of them, there is no die-to-database inspection solution. The capabilities described in this paper (the XPE die-to-database algorithm working with the KLA-Tencor TeraStar SLF87 system) were developed precisely because no tool in the industry was capable of meeting all of these requirements. The industry was in urgent need of a die-to-database system that is capable of inspecting reticles for the 90nm node at high sensitivity, with a low false defect count for a full plate inspection. XPE, the new die-to-database inspection algorithm for the TeraStar SLF87 (XPE-87), has been developed for the inspection of 193nm lithography reticles to be used for the 90nm node and beyond. XPE-87 uses new and improved methods for database rendering, defect detection and image contrast adjustment. The algorithm can accommodate the reticle characteritics, inspecting plates with complex features and addvanced Sub-Resolution Assist Features (SRAFs) at high sensitivity and low false defect count. Thanks to enhancements to system hardware and light calibration routines, the algorithm is very effective at inspecting 90 nm node ArF half-tone reticles. XPE-87 has been characterized with 193 nm and 248 nm EPSM versions of Spica, a new programmed defect test reticle. In the presence of complex OPC, results show a substantial improvement in sensitivity compared to previous die-to-database inspection algorithms. The new algorithm has also been used to inspect a variety of 193nmEPSM, 248 EPSM and chrome on glass production reticles. The results show significant improvement for the inspection of 90 nm node half-tone reticles including plates with SRAFs. Simulations were performed to verify the XPE-87 potential for defect detection. Evaluating changes in signal profile due to the presence of defects, a comparison was performed between the aerial profile of the XPE-87 at UV inspection aerial image and the wafer print aerial image at 193 nm. The results, show a larger signal for defects in small lines.

The inspection of alternating phase shifting masks is still one of the major challenges in state-of-the-art mask making. Main issue is that phase defects cannot easily be identified by inspection systems using an inspection wavelength different form the target exposure wavelength. The paper presents inspection results using the Aera193, an aerial image based mask inspection system.

An electron beam technology for repair of Next Generation Lithography masks is described. Deposition of missing material in clear defects is shown with different material characteristics. Etching of opaque defects is demonstrated. The superiority of the electron beam technology to the well established and widely used focused ion beam techniques is discussed. Electron beam repair avoids the unacceptable transmission loss which is generated by focus ion beam techniques especially for 193 nm and 157 nm lithography by Ga-ion implantation. Shrinking dimensions of printable defects require higher resolution than ion beams allow, which is, however, obtained routinely with electron beam systems. Specially designed lenses having low aberrations provide outstanding better signal to noise ratio than ion beam systems. Results on deposition and etching of NGL mask relevant materials like TaN, SiC, Mo/Si, and silicon dioxide is demonstrated. In general 1 keV electrons and a low electron current were used for the etching processes.

Repairing mask defects with Focused Ion Beam (FIB) of gallium often results in a gallium-implanted area due to scan. This implanted layer reduces the light transmission by up to 10 ~ 30 percent, depending on the wavelength. This effect of localized transmission loss becomes printable at the extremes of focus-energy matrix of wafer printing. The existing methods for the gallium removal give rise to quartz damage, side-etching or critical dimension (CD) variation. We propose a mild and new gallium-removing clean process. This process is based on the concept of gallium chelation with designed water-soluble polymers attached with several ligands for chelation. After our CHP1011 post-treatment, from 193nm MSM (Microlithography Simulation Microscope) analysis, the intensity of the scanned area can increase from 88% to 97%. The CHP1011 treatment can enhance the intensity of the repair area by 20% and CD by 15% from 193nm MSM simulation.

Carl Zeiss is currently in the final phase of an AIMS 157 development program in cooperation with Selete, Infineon and International SEMATECH. Based on Carl Zeiss' proven AIMS (Aerial Image Measurement System) technology, the new tool can optically emulate the aerial image generated in any given 157 nm scanner. Beta tools will be shipped throughout 2003. In this work the AIMS fab 157 hardware concept will be described. Latest measurements show that compared to first measurements CD repeatability and illumination uniformity could be significantly improved.

As it is becoming clear that the 65nm node lithography would have no other alternative than "193nm" reinforced with all the possible RETs, "tricky" masks such as Alternating PSMs, Chromeless masks, or Enhancer masks might become inevitable. Most of the "tricky" masks will need the quartz substrate to be etched to give the phase shift. This means that an etching process without an etch-stop or an interface between different materials should be applied. We evaluated Qz etching process and optimized etching condition. Phase shift measurement system (λ 248 nm) and atomic force microscope were used for our measuring Qz depth and profile. And we can measure narrow space to 0.2 um size. As a result of optimized condition, Qz depth uniformity is 3sigma 1.5%, cross section is vertical sidewall and rectangular corner, and linearity error is 4.5% with isolated space and 9.0% at hole. And, we checked this linearity error does not affect so much to wafer printing, using aerial software simulation.

LEEPL is a new electron beam exposure technology proposed in 1999. But, fundamental technologies used for LEEPL had been proposed and proved over the past one or two decades. By using existing technologies effectively, LEEPL can be developed in a short period. Fortunately, contact holes less than 100nm are required for 65nm-node lithography. We have the specific target for early implementation of the device fabrication. This paper describes the imaging capability, the image placement accuracy and the process application.

The placement-error correction for low-energy electron-beam proximity-projection lithography (LEEPL) has been demonstrated to enable the overlay accuracy of 23 nm that meets the requirement for the 65-nm node. The overlay accuracy for LEEPL-ArF mix-and-match lithography has been analyzed, focusing separately on the intra-field error, the inter-field error, and the dynamic fluctuation over different wafers. It has been found that the intra-field error, mainly due to the distortion of a 1x stencil mask, can be effectively corrected for by using the fine deflection of the electron beam, a unique capability of the LEEPL exposure equipment. In addition, the inter-field error can be suppressed by correcting in real time for the magnification error of each chip detected by the die-by-die alignment system. The dynamic variation in the total overlay error is also small, and the overall alignment accuracy is fairly compatible with the preliminary overlay budget.

We focus on stencil mask technologies for the next generation lithography (NGL) options such as electron projection lithography (EPL) and low energy electron-beam proximity projection lithography (LEEPL). For the production of high-quality stencil masks, we selected silicon-on-insulator (SOI) substrate as desirable stencil mask material because of its availability and quality. We showed how the membrane stress varies with dopant concentration and our proposed theoretical prediction on stress dependency on dopant concentration is consistent with experimental data. From the experimental data and prediction, doping method using SOI substrates proved to be able to produce membranes with stress of less than 10 MPa. We also presented how the out-of-plane distortions (OPD) within a subfield depend on the doping profile and cantilever beams with a length of 200 um remained flat. And then we measured the image placement (IP) errors within a subfield on a 200-mm EPL mask, which was less than 20 nm. Finally we employed the doping method to LEEPL mask and presented stress data. Therefore, we confirmed the doping method using SOI substrate is proper approach to fabricate low-stress stencil masks for EPL and LEEPL.

In electron-beam projection lithography (EPL), the proximity effect is more complicated than in conventional direct electron-beam writing. The correction of this effect uses pattern-shape modification because dose adjustment is not possible. Moreover, large sub-field transcription produces non-uniform beam blur due to optical aberration and local and global Coulomb effects. This large beam blur requires sophisticated correction depending on pattern features and layout over a very short range as well as pattern density over a backscattering range. In response to these issues, the authors have developed a flexible and precise correction method for the proximity effect under various conditions of beam blur, LSI process, and pattern arrangement. It features (1) multiple pattern-area-density maps, (2) look-up tables classified by pattern features and layout, and (3) a fast calculation algorithm for the iteration process of optimal bias. The developed method (running on four PCs with 2.4-GHz CPUs) attains a processing time of 55 min by using a bias map for 12-GB LSI flat data in 2000 sub-fields. An example of pattern classification by this method showed the usefulness of pattern bias for each individual pattern edge over a short range. It is concluded that the developed correction method is useful not only for proximity effects, including the Coulomb effect, but also for various process effects in mask making with precise CD control.

Scanning-electron microscopes designed for critical dimension (CD) measurement (CD-SEMs), which operate in a reflection mode, are commonly used in photomask quality assurance. However, such CD-SEMs are not always suitable for CD measurement of electron beam (EB) stencil masks such as electron-beam projection lithography (EPL) masks and low-energy electron-beam proximity projection lithography (LEEPL) masks. A dual-mode CD-SEM, which can operate in a transmission mode besides in a reflection mode, was recently developed by HOLON. The performance of the tool will be reported. Two EPL test masks with a 2-μm-thick Si scatterer and one LEEPL test mask with about 1-μm-thick absorber were prepared. The EPL masks have 1:1 lines-and-spaces (L&S) patterns and isolated spaces, all varying from 200 to 1000 nm in designed size. The LEEPL mask has 1:1 L&S patterns ranging from 80 to 550 nm. The masks were observed at an acceleration voltage of 5.5 kV with no bias voltage and a current of 10 pA. The dual-mode CD-SEM is found to have the following characters: (1) short-term repeatability and long-term repeatability less than 2 nm in both modes, (2) compatibility with a photomask CD-SEM in the reflection mode, (3) coincidence of the CDs measured in the transmission mode from the front side and back side within 3.0 nm for stencil patterns with a sidewall angle larger than 89.8 deg, and (4) capability of measurement at least down to 80 nm. Therefore we conclude that the dual-mode CD-SEM is applicable for measurement of CDs of EB stencil masks.

The Extreme Ultraviolet Lithography (EUVL) technology is transitioning from the basic research and technology demonstration phase into commercialization. All key EUVL system modules have been demonstrated with an Engineering Test Stand (ETS) and the system has been used to provide the basic learning for developing commercial EUVL tools. Full field scanned printing has been demonstrated. Full field masks have been produced and methods have been demonstrated for defect repair for both mask blanks and for patterned masks. Major European, Japanese, and US consortia in partnership with over 100 industrial companies are supporting the establishment of the EUVL infrastructure. The remaining challenges have been identified and laboratory and industrial support are continuing to reduce the risks for developing beta and production tools. Production tools are expected to be introduced in the 2007 time frame to support aggressively implementation of 45 nm node geometries with volume production support for the 32 nm node in 2009.

It is proposed that at-wavelength EUV mask inspection system based on EUV microscope, which is the best way to observe the mask directly. Using this system, preliminary experiments to examine the pattern inspection of EUVL mask is carried out. EUV microscope has a capability to resolve 50 nm lithographic node finished EUVL mask. We confirmed that at-wavelength microscope rather than SEM is both powerful and useful for evaluating the mask fabrication process for EUVL. Furthermore, it is find out that the contrast of the mask images observed by EUVM influenced by the absorber material. As the result, important information of the finished EUVL mask can be obtained utilizing EUVM, which is very important tool for the finished EUVL mask inspection.

EUV mask technology poses many new challenges on mask manufacturing processes. One crucial manufacturing step is the patterning of the EUV absorber. Although in the first concepts a Chromium film is used as absorber, increasing demands for shrinking feature sizes will run Chromium out of steam. Due to the necessary oxygen content of the chromium etch plasma and the isotropic etch mechanism for chromium an etch bias of several 10 nm occurs. This results in limitations for the minimal feature size, for which reason a new absorber material has to be developed. The most promising candidate is Tantalum Nitride TaN, which in contrast to the isotropic Cr-etch process, gives the possibility of applying a more anisotropic etch utilizing higher ion energies and sidewall passivation. In this work a plasma etch process for TaN masked with positive CAR resist was developed on masks including a SiO₂ buffer layer. Before running the experiments for process characterization, an endpoint detection solution by OES for very small open areas was developed utilizing principal components analysis (PCA). Additionally, an experimental matrix was set up varying bias power, source power and pressure. The DoE experiments were analyzed with respect to etch selectivities, etch bias, etch polymer formation, sidewall angle, iso-dense bias and linearity. After characterisation of the experimental results, optimized process conditions are discussed. We show that this process is capable of resolving feature sizes below 100 nm.

PATACON-EPL is a software product for converting semiconductor mask CAD data to the EB data of masks for EB steppers. This software has several functions, such as pattern placement corresponding to the structure of masks for EB steppers, complementary division for stencil masks, stitching for deforming the shape of a portion for connecting divided portions, proximity effect correction, machine control data generation, mask inspection data generation, and alignment mark insertion. This software operates in the environment in which several to some hundreds of Linux PC's are connected by a high-speed network.

EPLON is the name of a system that we have been developing as a data conversion system for EPL masks in order to meet the requirements of EPL stencil masks. In our paper we presented in PMJ2002, we proved that our system could convert the whole chip data. However we still had some problems to overcome, one of which is a problem of conversion time and another issue is a data volume problem. This paper presents the features of our multi process computation method and the data compaction with building a hierarchy from the flattened data.

We developed 200-mm stencil masks for electron projection lithography (EPL) by using silicon-on-insulator (SOI) substrates. Stress of a 2-μm-thick single crystalline silicon membrane, where patterns were fabricated as openings, was controlled around 10 MPa by adjusting concentration of impurities doped into the SOI layer. Boron and phosphorus were investigated as doping impurities, and it was confirmed that doping both elements were capable of stress control. For forming struts that supported the thin membrane, a time multiplexed etch method was applied. Control of the deep etch parameters made it possible for the SiO₂ stopper layer not to be etched through even if its thickness was sub-microns. To fabricate pattern openings in the membrane, reactive ion etching with high-density plasma was applied and lines down to 140 nm was fabricated in a 200-mm mask. Image placement distortion within a subfield was measured across the 200-mm mask and magnitudes of the image placement distortion were typically ~15 nm (3σ). A 200-mm EPL stencil mask having Selete's actual 70-nm design-rule system on chip (SoC) device pattern was successfully fabricated. We confirmed that the SOI substrates had potential abilities as initial material for 200-mm stencil mask fabrication.

PATACON-LEEPL is a software product for converting semiconductor mask CAD data to the EB data of masks for LEEPL transcribing devices. This software has several functions, such as pattern placement function corresponding to the structure of the LEEPL mask, which is different from the mask for optical steppers, complementary division function for stencil masks, correction of distortion due to mask internal stress, and alignment mark insertion. This software operates in the environment in which several to some hundreds of Linux PC's are connected by a high-speed network.

We have prepared 100-mm and 200-mm 1X stencil masks for low energy electron-beam proximity projection lithography (LEEPL) using silicon on insulator (SOI) substrates. We chose 200-mm without frame type format for production mask and 100-mm with NIST-like frame type for developing. And we employed COSMOS (complementary stencil masks on strut-supports) structure proposed by SONY to suppress in-plane distortion (IPD) of membrane. Our 100-mm mask contains 70-nm node device patterns. The critical dimension (CD) uniformity of a 100-nm width line patterns was 5.6 nm in range within 20-mm square area. The CD linearity of the line patterns was 5.5 nm in range throughout the range of 80- to 300-nm width. In our 200-mm mask, 100-nm width line patterns and 150-nm width hole patterns were successfully fabricated within 46-mm square area.

Low energy electron proximity projection lithography (LEEPL) has three types of mask formats. One of them, LEEPL 6025 square format, is so designed that electron-beam writers for photomasks can accommodate it. LEEPL 6025 square format blanks manufactured by three methods were evaluated in laying stress on cutting and bonding. The starting substrate was a 200-mm silicon-on-insulator wafer composed of a 2-μm-thick silicon layer, a 1-μm-thick SiO₂ layer, and a 725-μm-thick base silicon. Membrane wafers were made after dry etching of the backsides of the starting substrates. They were cut and bonded to frames. Ceramic SiC and a Si-base material were used for the frame. Soldering and other thermal methods were employed for bonding. The findings are: 1) No membranes were broken in cutting and bonding, 2) Chipping was observed after cutting, which requires some edge treatment like edge beveling, and 3) The flatness of the membrane wafer was reduced from 87 to 13 μm by bonding. In conclusion the 6025 square format blanks were successfully manufactured by three methods and evaluated in the first time.

We propose the efficient on-site use of a 1x stencil mask for proximity electron lithography (PEL) for controlling image placement (IP) and critical dimension (CD). It has been demonstrated that the integrated approach to the IP-error correction on the mask-fabrication level using the data manipulation and the mask-exposure level using the deflection of an electron beam (EB) can meet the requirement for the overlay accuracy in the 65-nm technology node. Also, the time-dependent variation in mask CD due to EB-assisted contamination growth can be managed by using the combination of the dose control and the periodic dry cleaning of the mask.

The critical-dimension (CD) performance and the printability of 1x stencil masks used for low-energy electron-beam proximity-projection lithography (LEEPL) have been studied by using the LEEPL β-tool. The CD uniformity and the line edge roughness on the mask are 6.0 nm and 3.5 nm in 3σ, respectively. It has been found that the fidelity of the etching process is so high that the optimization of the electron-beam writing process is critical to perforate high-quality patterns. The mask error enhancement factor evaluated over 80-100 nm lies is nearly unity, demonstrating the excellent fidelity of image transfer from the mask to a wafer. The critical defect sizes are 14.5 and 22.8 nm for the protrusions on the edges of 100-nm lines and the 150-nm contact holes respectively, implying that defect inspection is a challenge. The current achievements and the final targets in the 65-nm node are compared to assess the gap that must be bridged.

The practical methods for splitting line-and-space (LS) patterns and large rectangles into two complementary portions have been developed for the fabrication of stencil masks. The critical length for LS patterns can be determined from the finite-element modeling of the patterns under the external force acting up them in the wet cleaning of the mask. The optimal way of placing the split portions over the mask has also been demonstrated. On the other hand, a large pattern should be split in a step larger than half the shorter side of the figure. Since the methods are based on the simple and fast modeling, the flexible criteria as a function of design rule can be set in the splitting algorithm.

The exposure contrast (at wavelength contrast) on an extreme ultraviolet (EUV) mask has been evaluated by an experimental reflectivity measurement and an optical simulation. The experimental contrast showed good agreement with the calculated one for an EUV mask blank with TaBN absorber. The exposure contrast could be precisely estimated for an EUV mask using the simulation. Further, this simulation was used to evaluate the impact of absorber materials (TaBN, Cr and CrN) and 50-nm-thick buffer layers (CrX, SiO2, Ru and C) used to achieve thinner absorber stack. A mask composed of the TaBN absorber and the Cr-based buffer layer showed was the thinnest to achieve thinner absorber stack. A mask composed of the TaBN absorber and the Cr-based buffer layer showed was the thinnest to achieve a contrast of 100, at 81.3-nm. The TaBN absorber and the Cr-based buffer layer were found to be more suitable materials for obtaining lower aspect ratio.

Because the capabilities for experimental studies are still limited, a predictive simulation of EUV lithography is very important for a better understanding of the technology. One of the most critical issues in EUV lithography modeling is the description of the mask, especially including multilayer defects. A new model for the characterization of defects in the multilayer of an EUV reflective mask is presented. The mask is divided into an absorber part, which defines the features on the mask, and a multilayer part, which determines the reflectivity of the mask without absorber. Since the height of the mask features is large in comparison to the illumination wavelength, the computation of the absorber part is performed by a finite-difference time-domain (FDTD) method. Because of the limited range of illumination angles with a high reflectivity and the limited diffraction efficiency of the multilayer, the computation of the reflectivity of the defective multilayer is performed by the Fresnel-method. The defect topography is taken into account by means of correcting the phase and the angle of incidence. For the complete computation of the reflected light from the EUV mask a coupling of the two methods is realized. Thus, the model can be applied to two and three dimensional defects and masks. The impact of the defects on the mask reflectivity, the near field and the aerial image is analyzed. Typical mask structures, such as 2D-lines and 3D-dots with various defects, are investigated. First comparisons with another simulation model, the MMFE method, are presented.

The dependence of printability on the thicknesses of the TaN absorber and Ru buffer layers is investigated using 22-nm-wide semi-dense line patterns. Simulations are carried out using two sets of thicknesses corresponding to optical densities (OD) of 2 and 3. Thicker layers (i.e. larger OD) are found to yield a smaller linewidth variation when the exposure light is focused on the wafer. However, they also enhance the shadowing due to off-axis illumination on a mask, which degrades the pattern edge contrast of the aerial image under defocused conditions. Estimations of the linewidth variation and the pattern position shift for a focal latitude of ± 50 nm show that thinner absorber and buffer layers (i.e. OD = 2) are more practical than thicker ones. An examination of the reflectance loss of the Si cap layer on a multilayer blank due to oxidation reveals that it is essential to select an appropriate initial thickness of the Si to ensure sufficient reflectance after the Si is oxidized by contaminants.

We use the gradient of the image slope and gradient of the edge placement error (EPE) in order to improve both slope and EPE during OPC. The EPE gradient taken with respect to edge position is normally called MEEF or the MEEF matrix. Use of the gradient of image slope with respect to change in edge position was introduced by Granik as the “contrast matrix.” Whereas traditional OPC techniques focus on EPE alone (pattern fidelity), we broaden the scope of OPC to maximize slope for improved image robustness and to maximize process window.

Variations in manufacturing process introduce uncertainties in model based optical proximity correction. Discrepancies may arise between the model description and the actual manufacturing condition. Optimal mask correction should minimize the sensitivity of line width variation as the lithography process variables change within the accepted range. In this paper, the effect of defocus on OPC mask and wafer patterning is investigated using a physical pattern transfer simulator, LithoScope. We evaluate the impact of defocus on a set of test patterns and on real circuit layout. We propose to control defocus effect by design centering and physical model-based verification.

A double exposure technology, SPADE (Single Photo-resist And Double Exposure), utilizes the total accumulation resist energy exposing by different masks for pattern development. This "SPADE" process is a double exposure procedure that including resist coating, baking, first mask exposure, and second mask exposure and developer. This paper examines the process condition affecting the performance of ROM codes. We found that the first exposure with pre-code dense pattern is one of most critical parameters to affect the performance of the CD bias and resolution. Additionally, the second mask for real code pattern developer was also investigated in different mask CD size split. The final ROM code CD behavior is determined by both of the two masks. The results of these studies are discussed in term of mask type, exposure dosage, mask sizing and overlay sensitivity. Experimental results indicate that the iso-dense CD bias is smaller than traditional method. The energy latitude (E.L.%) also shows double than that of traditional ones.

Alternating phase shift mask (altPSM) as a strong resolution enhancement technique is increasingly required to meet the tighter lithographic requirements on gate critical dimension (CD) control, depth of focus and low k1 applications in full chip patterning of logic and memory devices. While the frequency doubling mechanism of altPSM benefits the quality of imaging, the inherent intensity asymmetry between phase shifters, or image imbalance, causes line shift. The effect of mask topography on electromagnetic wave propagation must be compensated in practice. Various designs of mask structure for correcting the intrinsic imaging asymmetry have been extensively studied. In this paper, we discuss several image imbalance correction methods for hidden phase edge altPSM architectures, including chrome undercut, shifter width sizing, sidewall chrome alternating aperture mask. We compared both hidden phase edge as well as exposed phase edge altPSM in terms of scalability, image correction effectiveness, and manufacturability for 90-nm, 65-nm technology nodes and beyond. Specifically, we define the altPSM architecture scalability in terms of three key components: 1. Mask manufacturability, design layout complexity, and effectiveness of image balance correction, 2. Mask patterning resolution, pattern fidelity, image placement, CD & overlay control at both chrome and glass levels, 3. Tightening quartz etch process control for given phase error tolerance. Applications of altPSM technology to line/space, hole, and phase shifted assisted features patterning with various altPSM architectures are also addressed.

In our previously published work, we investigated alternating-aperture PSM image intensity imbalance as function of various mask and optical parameters using rigorous electro-magnetic field (EMF) simulations. Results suggested that the imbalance could be effectively compensated through application of an optimized combination of undercut and a constant phase-shifter bias. In the effort of development and implementation of a production-ready image imbalance correction methodology, it is important to validate the accuracy of simulation-based predictions through correlation of results to experimental data. For this purpose, a test reticle containing various mask parameters as variables was designed and manufactured. The experimental data was obtained from SEM measurements of the exposed wafers, and results were compared to rigorous EMF simulation data. Based on results obtained, we propose and validate an image imbalance correction methodology to be implemented within the framework of the PSM - OPC manufacturing flow.

As IC fabrication processes are maturing for the 130nm node, silicon manufacturers are focusing on 90nm device manufacturing at ever-lower k₁ factors. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at similar k₁ near 0.3. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique. For low-volume, the high mask cost of Alt-PSM discourages its use. What are the most sensible KrF lithography patterning options at k₁ = 0.3? For single exposure mask solutions at the 90nm node using KrF, there are two leading candidates: 6% attenuated PSM (Att-PSM) and Chromeless Phase Lithography (CPL). In this work, we explored and compared these two options in terms of the best achievable process latitude for patterning poly gate layer. First, we analyzed the diffraction patterns from 6% Att-PSM and CPL mask features and identified the optimum transmission for various pitches. Next, we examined the two options from a mask making perspective, accessing mask manufacturability, phase and transmission error control, defect sources, etc. In this paper, we describe how hybrid CPL can be used as a variable transmission mask to produce the best through pitch imaging performance and a practical implementation method for mask manufacturing.

Chromeless Phase Lithography (CPL) is one of the promising RETs for low K₁ optical lithography. However, there are remained issues in CPL mask manufacturing, such as phase defect, which can be generated during quartz dry etching process. In CPL mask technology, the traditional defect printability specification is no longer adequate. This paper investigates to understand the tolerance of the CPL in view of phase defect specification. We studied to find out specifications for phase defect in CPL mask. Three-dimensional topography is used in the phase defect simulation. Based on the simulation results, programmed defect mask is made to evaluate phase defect printability by measuring aerial images with AIMS. Also the inspection sensitivity for quartz phase defect was evaluated with current inspection tool.

Phase Shift Masks (PSMs) have been widely used in the photomask industry for nowadays. Among several types of PSMs, Alternating Aperture PSM (AAPSM) allows for better resolution within other advantages. This paper deals with micro-trench formation during quartz etching. Micro-trench can produce distortion of the light intensity and lead unwanted results on wafer. Several experiments are performed with respective etch conditions; fluorine (F) gas species, gas flow rates, bias powers, and substrate temperatures while other conditions are fixed. Quartz etching is processed with Inductively Coupled Plasma (ICP) system. Etched morphologies are observed by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM), and a surface profiler to select the best condition as functions of etch parameters. Results show that bias power is the most important factors to decide quartz surface morphologies. Finally, mask image is simulated by AIMS system under given condition.

From 90nm node and beyond, all of the advanced silicon wafer manufacturing processes are likely to heavily depend on the use of PSM. Two styles of PSM have been considered favorably for both 90nm and 65nm nodes, one is the 6% attenuated PSM and the other one is Chromeless Phase Lithography (CPL) mask. At 65nm node, both of the MoSi-based attenuated PSM and CPL mask are required to be etched into quartz substrate to achieve the desired pi-phase shift. In addition to the demand for very tight top-down mask CD control, for dry-etched process, there are two critical factors can have a significant impact to wafer CD control. They are the etch depth control through feature pitch and the overall etch slope profile. Both contribute to the phase variation. The phase variation degrades the overlapped process window and sufficient phase error can act like spherical lens aberration. This will no doubt impact the wafer imaging performance. In this work, we characterize our dry-etch process by using an orthogonal experiment method and then examine the performance of the optimized recipe by CD metrology, phase uniformity, and actual wafer printing result.

Mask cost is one of crucial issues in device fabrication, especially in SoC (System on a Chip) with small-volume production. The cost mainly depends on productivity of mask manufacturing tools such as mask writers and defect inspection tools. EPL (Electron Projection Lithography) has been developing as a high-throughput electron beam exposure technology that will succeed optical lithography. The application of EPL technology to mask writing will result in high productivity and contribute to decrease the mask cost. The concept of a mask pattern generator employing EPL technology is proposed in this paper. It is very similar to EPL technology used for pattern printing on a wafer. The mask patterns on the glass substrate are exposed by projecting the basic circuit patterns formed on the mother EPL mask. One example of the mother EPL mask is a stencil type made with 200-mm Si wafer. The basic circuit patterns are IP patterns and logical primitive patterns such as cell libraries (AND, OR, Inverter, Flip-Flop and etc.) to express the SoC device patterns. Since the SoC patterns are exposed with its collective units such as IP and logical primitive patterns by using this method, the high throughput will be expected comparing with conventional mask E-beam writers. In this paper, the mask pattern generator with the EPL technology is proposed. The concept, its advantages and issues to be solved are discussed.

The severe mask specification makes mask cost increase drastically. Especially, the increase in the mask cost deals ASIC businesses a fatal blow due to its small chip volume per product. Pattern writing cost has always occupied the main part of the prime mask cost and the emphasis of this is still increasing. This paper reports on a Photomask Repeater strategy to be a solution for reducing mask cost in pattern writing, comparing with conventional EB system.

In a joint-development, Rohwedder and Osmic have designed and built a low-defect dual-ion beam reactive-sputtering tool. The tool has been specifically targeted for developing low-defect lithography mask photoblank coatings intended as DUV absorbers and phase-shifting films. The Osmic/Rohwedder collaboration will continue into NGL -- the present tool also serves as an R&D platform for EUVL mask blanks. The deposition tool and robotic substrate handler have been integrated and delivered to Osmic in the 2nd quarter of 2003. In this paper, we present initial capability for production of thin-film lithography coatings, including spectrophotometric performance, defect levels and film uniformity. Future reports will share results from more in-depth process development and optimization.

In our previous study, a-Si thin films were suggested as a passivation layer to prevent the degradation of Si-O-N-F films that were phase shift materials for 157 nm optical lithography. However few studies about the optical properties of a-Si in the deep ultraviolet (DUV) region have been reported. a-Si thin films having thickness of less than 25 nm were deposited using dc magnetron sputtering with a mesh to ensure the uniformity. The thickness, composition and optical properties of a-Si were analyzed with SEM, AES, UV spectroscopy and a VUV spectroscopic ellipsometer. Using the results of spectroscopic ellipsometry (SE) analysis, optical properties, including absorbance, transmittance, optical band gap and optical constants (n, k), of a-Si films with different thickness (11 to approximately 25 nm) were analyzed using the model of EMA(a-Si+SiO)/a-Si (EMA:effective medium approximation). From the SE analysis of a-Si films, we onfirmed that a-Si film with high transmittance in DUV could be used as a passivation layer of Si-O-N-F films.

As minimum feature size of device shrink down below 100 nm, the process margin for the mask fabrication reduced dramatically. Mask makers are enlisting equipment and material suppliers in their efforts to achieve wide process margin from existing processes. One of the most promising methods is thinning Cr thickness as low as possible. However, briging the thin Cr blank into mass production line could cuase some problem for advance photomask fabrication using 50 kV electron beam writing tools. In this paper, we verified the feasibility of Cr film ranged from 400 Å to 1000 Å. The results categorized into two sections. At first, we verified the writing property change with thinning Cr thickness and then investigated the etching characteristics. As a result, we found that Cr thickness don't affect writing properties regardless of Cr thickness. However, the thinner Cr blank represented superior etching characteristics to a conventional one. It showed low etching bias and loading effects. From these results, we concluded the thinner Cr blank could not only make the process wider but also improve the mask quality.

The critical dimensions (CD) change by the process delay is the most critical issue to apply the chemically amplified resists (CAR) for photomask fabrication. In the photomask fabrication processes, the resist should have both post coating delay (PCD) and post exposure delay (PED) stability, while keeping higher sensitivity. To achieve this requirement, overcoat process has been examined for the purpose of CD stabilization in CAR process for photomask manufacture. The material, which consists of hydrophobic polymer and PAG, was used for the overcoat in this study. Consequently, it has become clear that pattern formations have been possible without unnecessary thickness loss. Moreover, it has been proved that the overcoat shows the effect of controlling CD change and improvement of CD uniformity. From these results, it is thought that the overcoat process is promising for the size stabilization in photomask manufacture for devices less than 90 nm.

DUV (Deep Ultra-Violet) laser reticle writers were released to the market for advanced reticle fabrication in 2002, AZ-DX1100P resist (for KrF lithography) has historically been employed for these tools. To respond to further high-end requirements, a new resist more friendly to DUV reticle fabrication is needed. FEP171 is a positive-type CAR (Chemically amplified resist) developed for EB reticle fabrication, which is sensitive to DUV as well. In this paper, we have investigated the applicability of FEP171-coated blanks for DUV reticle fabrication. As the results show, FEP171 could achieve 200 nm patterns by DUV exposure. FEP171 blanks showed superior performance in resolution and profile as compared to AZ-DX1100P. FEP171 blanks are promising for DUV reticle fabrication as well as EB reticle fabrication.

For the latest photomask fabrication, better critical dimension (CD) control and pattern fidelity to design size are required. According to the latest ITRS roadmap, masks for the 90 nm technology node should have CD uniformity of 6~8nm (3σ). Moreover, CD control is particularly critical for isolated opaque lines, such as those found in gate layers, whose loading is primarily clear field. The high acceleration voltage electron beam (EB) systems that employ variable shaped beams (VSBs) are used for mask writing due to their high throughput. To minimize write time and fogging effects, and to control mean CD and improve CD uniformity for mask production, it is well known that negative tone resists enable better VSB mask writing system performance. In these circumstances, positive and negative tone chemically amplified resists (CARs), FEP171 (Fuji Films) and FEN270 (Fuji-Films), were evaluated empirically for mask making. We investigated and compared resolution, sensitivity, resist profiles, CD variation vs. exposure dose, proximity effect correction (PEC), fogging effect, pattern fidelity, and so on. Furthermore, write tool data volume and throughput, defect trends, and other process parameters on the positive and negative tone resists were evaluated and compared by applying test patterns.

Negative-tone chemically amplified resists MES-EN1G (JSR), FEN-270 (Fujifilm ARCH), EN-024M (TOK) and NEB-22 (Sumitomo) were evaluated for binary mask making. The investigations were performed on an advanced tool set comprising a 50kV e-beam writer Leica SB350, a Steag Hamatech hot/cool plate module APB5000, a Steag Hamatech developer ASP5000, an UNAXIS MASK ETCHER III and a SEM LEO1560 with integrated CD measurement option. We investigated and compared the evaluated resists in terms of resolution, e-beam sensitivity, resist profile, post exposure bake sensitivity, CD-uniformity, line edge roughness, pattern fidelity and etch resistance. Furthermore, the influence of post coating delay and post exposure delay in vacuum and air was determined.

In this paper, a process established with a positive-tone chemically amplified resist (CAR) from TOK REAP200 and Fujifilm Arch FEP171 and 50kV MEBES system is discussed. This TOK resist is developed for raster scan 50 kV e-beam systems. It has high contrast, good coating characteristics, good dry etch selectivity, and high environmental stability. In the mask industries, the most popular positive tone CAR is FEP171, which is a high activation energy type CAR. REAP (Raster E-beam Advanced Process) 200 is low activation energy type and new acetal protecting polymer. In this study, we compared to these different type resists in terms of contrast, PAB and PEB latitude, resist profile, footing, T-topping, PED stability, LER, Global CDU (Critical Dimension Uniformity) and resolution. The REAP200 Resist obtained 75nm isolated lines and spaces, 90nm dense patterns with vertical profile, and a good stability of delay time.

As the requirement of specification on photomask continues to be tightening with advanced logic and memory devices, the combined process of chemically amplified resist (CAR) and high acceleration voltage e-beam writing tool is widely used to meet the resolution and throughput for advance photomask fabrication. It is well known that the post exposure baking (PEB) condition makes serious effect on the characteristic of CAR due to its de-protection reaction with thermal acid catalyzation. In this paper, we present the PEB temperature effect on pattern resolution such as line edge roughness (LER) and proximity effect correction (PEC) latitude that is practical limitation in the combined process of 50 kV writng tool and CAR resist. Our results show that LER and PEC lattitude are strongly dependent on PEB temperature due to resist contrast variation. At higher PEB temperature, increasing the contrast value can reduce the LER and it can increase the optimum PEC latitude.

Recently there has been significant interest in the using of chemically amplified (CA) resists for the mask making industry because of their high sensitivity, high contrast, and good dry etch resistance. Especially positive CA resists with high acceleration voltage E-beam systems are being become the main stream of making for advanced masks. However, the positive CA resists often make the issue of the CD uniformity degradation by the fogging effect at a high acceleration voltage (50keV) E-beam writing tool as writing for masks, which are having a high pattern density. In previous our paper, we have already confirmed that a positive CA resist shows the CD uniformity error more than 30nm by the fogging effect at the mask which is having above 40% pattern density, even if its CD uniformity error value is smaller than 50nm of ZEP. In this paper, we have described and studied for the performances of the negative CA resist at the 50keV e-beam writing tools in advanced mask making like logic device with high pattern density and we have compared with a positive CA resist at the 50keV e-beam writing tools. Furthermore, we have confirmed that the negative CA resist have an advantage what is in advanced mask making process like logic device masks with high pattern density at 50keV e-beam writing tool and they have been compared with the positive CA resist.

The features of optical proximity correction are becoming very aggressive as production technology migrates into 90nm/130 nm regime. The complicated optical proximity correction (OPC) patterns often result in un-repairable defects, a major yield loss mechanisms in a mask production line. Defect control is increasingly important. A methodology for identifying defect sources and reduction is demonstrated in this paper. The mechanisms and causes of defect formation could be determined with corresponding process step on the strength of sequence inspections. The cause of half-etched opaque defect on negative CAR process was found from PR fragment contamination of e-beam exposure step. After clean-up of e-beam chamber, yield was increased over 20%. Big pinhole defect and contact of AttPSM positive process was found on ADI step. The possible cause was poor CAR adhesion. These two type defects were decreased by modification of developing recipe, special on rinse step. Design experiment with Taguchi method was used to optimize the interactive recipe of plasma descum and rinse step on developing step of implanted layer. Average defect density was decreased from 0.99 to 0.27, and percentage of zero defect rate has been increased from 29.5 to 63.3%.

With shrinking feature sizes there is a growing demand for improved uniformity values and defect levels especially for aqueous develop during photomask processing. Standard nozzle systems with discrete dispense channels for applying the developer medium onto the photomask surface may cause non-uniformities. This results in characteristic imprints in CD-uniformity reflecting the nozzle design used during the develop process step. These can lead on the one hand to an increased number and various types of defects and on the other hand to variations in CD-uniformity. A new puddle nozzle design for the STEAG HamaTech's ASP5500 has been developed to address this issue. Instead of discrete dispense holes the developer medium is applied onto the substrate surface by a full-width film. This media film is applied uniform across the substrate and has low impact onto the photomask surface. By combining the new nozzle design with gas-less high volume dispense pumps a very uniform and defect-free dispense can be achieved. The uniformity and defect performance of the new film nozzle will be presented and compared to a standard dispense nozzle system. The study has been done on masks with Chemically Amplified Resist (CAR).

In Photomask Japan 2002 we reported a model of coating and drying process for the flat polymer (resist) film fabrication. The model models the process that polymer solution coated on a flat substrate by scanning technique, which is developed for LSI technologies at the next generation, is dried under reduced pressure. After above drying process, a resist film having a typical thickness profile that the edge of the film is thicker and just the region next to the edge's bump is thinner. Using the model, we numerically clarified the bumpy structure of the edge of a resist film depended on some essential parameters -- vaporization rate, diffusion coefficients coated solution thickness, intrinsic viscosity and so on. But the former model doesn't include the effects of a drop of temperature on the surface of a liquid film and the inside of it by latent heat and diffusion of heat by conductivity. But we cannot ignore these effects since a drop of temperature is essential in phase transition. And change of diffusion coefficients and viscosity by the drop of temperature has an important influence on the model. In this paper, we will report the modified model taking a drop of temperature on the surface of a liquid film and the inside of it by latent heat and diffusion of heat by conductivity and change of diffusion coefficients and viscosity by it into consideration and numerical results using the model.

As lithography pushes to the nanoline dimensions, even less drastic changes during photoresist processes can have a non-disregarding impact on proximity behavior, thus these changes can affect the optical proximity correction rules and models. In this study, after the descriptions of the modified mechanical method of rinse and dry processes and the model of etch simulation for dense and isolated lines, the impact on proximity behavior is described and analyzed by using the quantitative sensitivity of the pattern collapse and etch properties on the critical dimension. The effect for optical proximity correction rules and the characterization of the mask error enhancement factor are discussed.

Nowadays, the CD (Critical Dimension) control on masks manufacturing plays an important role in photolithography process for 90-nm node technology and below. The process performance of photolithography will degrade severely even when the mask CD error is small. One of the most important process-induced mask CD errors comes from the dry etching process. With the loading effect due to environment pattern variations, isolated and dense patterns have different etching biases. Furthermore, the loading effect can induce an overall CD variation called global loading effect contributed from the pattern density change in large areas and a CD variation on individual monitor pattern called micro-loading effect contributed from various feature dimensions in the near region. The micro-loading effect can also be classified as the “nearest spacing” effect which is dependent upon the space between the nearest neighbor pattern and the monitor pattern, and the “nearest neighbor” effect which is dependent upon the size of the nearest neighbor feature around the monitor pattern. All of these effects enlarge the total range of mask CD linearity and proximity errors. In this paper we report the result of the global loading effect and micro-loading effect by varying pattern densities and feature dimensions nearby. With the design of test pattern, the global loading effect and the micro-loading effect can be separated. The CD variation dominated by the micro-loading effect in the dry etching process is observed. This large etching bias change resulted from the micro-loading effect is consistent with the depletion of radical species in the narrow space during the etching process.

High resolution etching of MoSi for photomask processing places new requirements on etching processes. As resist features are sized to 100 nm and below, it is first necessary to duplicate these features first into a chrome over-layer. After resist is stripped, this chrome over-layer is used for etching MoSi. Both chrome and MoSi etched profiles require near-vertical sidewalls, good CD (critical dimension) uniformity, good linearity, and CD mean-to-target (MTT). Additional requirements of etched MoSi include minimal roughness on exposed quartz, selectivity to chrome and quartz, phase angle target and phase angle uniformity, etch depth global uniformity, and etch depth uniformity as a function of feature size. An ETEC integrated process is used for the application of resist, patterning, and all subsequent processing. Chemically amplified resist is patterned with the 50 kV MEBES Quadra or MEBES eXara raster scan electron beam writer, allowing for patterning of small features with vertical resist profiles. Plates are etched in a Tetra photomask etch system for projecting resist images into chrome and MoSi. Etch processes have been developed specifically for etching small features in order to meet the requirements of 65 nm node lithography. An optimized etch process window is capable of patterning MoSi features below 100 nm sizes with near-vertical sidewall, < 20 nm etch bias, and with similar profile and etch bias for lines and spaces between 100 nm and > 1 um. Excellent CD uniformity and CD etch loading performance are demonstrated. Micro-profilometry is employed to measure the MoSi etch depths of features of varying sizes, and to quantify the effect of loading on MoSi etch depth. SEM micrographs illustrate sidewall profiles resulting from small feature etching.

As the feature size of integrated circuits decreases, it is difficult to have a good resolution with an ordinary lithography technology. Resolution enhancement technologies (RETs), therefore, become prominent way to achieve better resolution. Among various RETs, Phase Shift Mask (PSM) can be one of the most useful technologies in these days and especially Chrome-Less Mask (CLM) or Phase Edge PSM (PE-PSM) is used for utilizing strong effect of PSM technology. In manufacturing the CLM or PE-PSM, the quartz layer of the photomask should be etched to 2480 in depth which is the equivalent value in phase, 180°. But quartz etch is one of the difficult processes in photomask manufacturing due to the absence of stopper layer. Moreover, the depth uniformity should be controlled within the tolerance of 5°. But there are etch rate variations from center to edge positions within the 6-inch mask area which originates from the deficit of plasma uniformity. As a result, phase deviation in those area occurs after quartz etch up to several degrees in phases and this problem makes the manufacturing of CLM or PE-PSM difficult. We thought there would be some relations between etch rate uniformity and hardware, such as focus ring which is used for confinement of plasma species. Various experiments, therefore, were executed with regard to the type of focus ring (shape, and height). As a result, the outstanding tendencies which show the relations, can be obtained. On this paper, the detailed descriptions of the experiments and their results will be presented.

As the 193 nm generation of steppers reaches the limit of its capability, alternating aperture phase shift masks (altPSMs) are necessary to extend the lifetime of these tools. The fabrication of a production-worthy altPSM requires that the quartz dry etch satisfy many conditions. The etched quartz features must not only show excellent phase uniformity, but they should have near vertical sidewalls and good etch depth linearity across a wide range of feature sizes. Surface roughness must also be low enough that transmission is unaffected. To this end, Unaxis USA performed a series of quartz photomask dry etch experiments utilizing a Unaxis Mask Etcher III. Etch depth uniformity and etch depth linearity are studied for each experiment. SEM cross-sections of the etched profiles and AFM analysis of surface roughness are also provided. Various models were constructed by IBM that demonstrate the importance of some of the etch responses, and the results from the optimized Unaxis process will be shown.

Uniform radical distribution in the etching plasma is essential to meet chrome critical dimension (CD) uniformity for future technology nodes on chrome masks. The Etec Systems Tetra photomask etch chamber utilizes an alumina focus ring in order to optimize the etch uniformity of the chrome mask by minimizing gas flow effects and shaping the radial distribution of the etching radicals over the mask surface. This paper describes a systematic investigation to optimize the current focus ring, in order to improve etch critical dimension uniformity. The focus ring (FR) optimization work was made possible by manufacturing a modular focus ring that allowed the geometry to be varied at different heights and diameters. The circular shape of the modular focus ring, along with the height and diameter combinations, has a large influence on the etch performance at the mask corners and edges. The underlying mechanism was investigated by modeling and simulation. Based on simulation results the focus ring geometry was varied and the optimum FR configuration was found. The critical dimension uniformity could be adjusted on uniformly patterned masks with different pattern loads to meet production specifications.

Front-end semiconductor lithography demands smaller size of patterns for 90 nm node and beyond, on both Si wafers and photomasks. In dry etching for photomasks, it needs tighter CD uniformity and loading effect. For meeting these demands the advanced NLD (magnetic Neutral Loop Discharge) mask etcher has been developed, because it could operate at lower pressure for reducing loading effect than conventional ICP etchers, due to the magnetic confinement of electron in plasma generation. In the NLD mask etcher, the configuration of plasma source was investigated for better performance and the etching condition was re-optimized for improving selectivity. Consequently, the selectivity of Cr/resist (ZEP-7000) was more than 1.6, compared with 0.95 in the previous condition. And also, the CD uniformity in Cr etching was improved to meet our target 6 nm (3 sigma) around 0.68 Pa. However, in the view of reducing loading effect, other condition that is lower pressure than 0.68Pa and adding Helium (HE) showed smaller global loading. Therefore, making a balance of uniformity and loading is necessary to get better performance in mask process. We also propose a basic condition using the advanced NLD mask etcher for dry etching a MoSiON shifter of atenuated PSM in this paper.

With alternating phase shift masks (altPSM) an enhancement technique is available to realize smaller design rules. Meanwhile the basic production process for this mask type is well known and established for 193nm technology development. The qualification of the masks is now in the focus of development work. Sensitive defect inspection is essential for the qualification of altPSMs. In addition accurate phase and transmission balancing measurement technique has to be applied. In this paper we are presenting a detailed defect printability study for sub-100nm feature size technology at 193nm wavelength. Programmed quartz defects with different shapes and sizes were designed. They were implemented in a lines/spaces altPSM design. The processed quartz defects were characterized with a scanning electron microscope and an arial imaging microscope system. The printing behavior of the defects was analyzed after wafer exposures. In addition the required sensitivity for the altPSM inspection was evaluated. Finally the inspection sensitivity was characterized and optimized with programmed and production like defects.

This paper reports a technique of reticle inspection incorporating the use of an image filter. In this technique, optical intensity distribution is calculated by optical simulation of electron beam lithography (EB) data or an image file obtained from a SEM photograph to evaluate the printability of defects on a reticle. When an image file is compared with the EB data, the image file has differences at the rounded corners as well as at the areas with defects because the image file is obtained from the reticle pattern. To reduce the differences, an image filter (or reticle filter), which simulates the pattern creation process on a reticle, was applied to the EB data. The simulated EB data is defined as the non-defect reference pattern. The optical intensity and critical dimension (CD) were then obtained. Image files of defects were obtained from the SEM photographs of reticle patterns having various sizes of defects. By applying optical simulation to patterns obtained from the image files, the optical intensity and CD were calculated and compared with those of the reference pattern, and the differences are evaluated. The evaluation results showed that optical intensity and CD changes fluctuate regardless of the size or type of defect. Correlation was confirmed between the differences in optical intensity and the CD changes in the defect area. It was thus concluded that defect printability can be evaluated by the differences in optical intensity obtained from image files.

As AAPSM becomes more widely utilized, the need for defect inspection sensitivity becomes more critical. In addition, accurate defect characterization must be performed to encompass new effects caused by glass defects. Historically, defect size and position have been the two characteristics that were examined when determining inspection tool sensitivity. Because of the nature of AAPSM defects, phase is a factor that must be taken into account. This experiment utilizes two distinct forms of defect characterization -- SEM sizing, and surface profilometry. Programmed defect test masks were manufactured for phase shifting properties at both 248nm and 193nm exposure wavelengths. The defects were also etched at multiple depths resulting in a variety of phase angle errors. Utilizing the two characterization methods mentioned above, the automatic defect inspection tool's sensitivity on multiple programmed defects will be investigated.

The semiconductor industry continuously shrink the linewidths and the smaller linewidths are easily affected by the defects. The defects have to be detected to prevent printed images on wafers. This paper will present the detection capability of current inspection machines for chrome defects on attenuated MoSiN layer and simulation results for the effect of chrome defect on attenuated layer. Two inspection machines based on i-line light source were used for comparison of detection capability for chrome defect on attenuated layer. The effect of chrome defect on attenuated MoSiN layer was evaluated with MSM 100 at 248 nm wavelength.

We have improved DUV laser reticle inspection system LM7000 for 90 nm technology node devices. To increase inspection sensitivity, we developed a reflected light inspection as a supplementary method to transmittance light inspection. We have also strengthened inspection algorithm to distinguish between real defects and very small features from optical proximity effect correction (OPC). Finally, we have improved reference image for die to database inspection. With the merit of short wavelength of LM7000 (266 nm), the inspection sensitivity of the high-transmittance half-tone phase shift mask (HTPSM) does not deteriorated so severely compared to that of binary mask. With the help of these series of improvements, LM7000 could shows inspection capability for OPC masks and HTPSM for ArF lithography. The inspection capability of LM7000 was proved with the programmed defect masks and printability experiment using ArF scanner.

The KrF12% tri-tone PSM (phase shift mask) was designed with the programmed defects on the chrome (Cr) and phase shift (PS) layers. From the lithography simulation, the PS defects, generated on the PS layer, were estimated to fluctuate the CD of the contact holes on the wafer more than the defects in the same size on the conventional EAPSM (half-tone PSM). The printability of the PS defects and Cr defects on the contact holes were investigated by the print-test on the wafer. The Cr residues on the PS layer slightly changed the CD of the contact holes on the wafer. The PS defects showed the great influence to the CD variation of the contact holes. The light calibration of the defect inspection was optimized to detect the PS and Cr defects. For the detection of the PS defects in the die-to-die inspection mode, the UV inspection system SLFX7 showed the high performance with the PS/SiO2 calibration, in which the boundary of the PS layer and SiO2 substrate was used as the light calibration point. The SLFX7 also available to detect the Cr defects in the die-to-die mode. For the die-to-database mode to detect the Cr defect, the KLA351, the visible light inspection system, was available by the Cr/PS calibration. The sensitivity of the SLFX7 and KLA351 was adequate for the Cr defects, however, that was not enough to the specification of the PS defects estimated from the print-test. The sensitivity of the SLFX7 showed a slight difference between the tri-tone and binary layout in the specific defect types.

The new repair of the clear defects on the half-tone PSM (EAPSM) was proposed. The Ga (gallium) ions were implanted by the FIB on the area adjacent to the carbon films formed on the clear defects. The Ga ion implanted area on the SiO₂ substrate showed the semi-transparency at the KrF and ArF wavelengths. The lithography simulations of the layouts designed for the defect-repaired area endorsed the concept of the new repair. The Ga ion implantation was optimized to the new repair by using the AIMS and AFM measurements for the transmittance and etched depth of the SiO₂ surface. The authors applied this method to the clear defects programmed on the KrF and ArF EAPSMs. The AIMS analysis showed that the deviation of the CD (critical dimension) of the defect-repaired regions on the wafer was within +/-5% to the non-defective reference at every defocused point. The new repair moderated the specification of the edge placement accuracy of the FIB processing compared to the conventional carbon film deposition.

As 90 nm devices enter into the pre-production phase, the quality assurance strategy of photomasks for those devices must be well established with the proper cost and turn-around-time in mind. Such devices will be manufactured with a state-of-the-art photolithography systems equipped with 193nm actinic light sources. Photomasks for these devices are being produced with the most advanced equipment, material and processing technologies and yet, quality assurance still remains an issue for volume production. These issues include defect classification and disposition due to the insufficient resolution of the defect inspection system, uncertainty of the impact the defects have on the printed feature as well as inconsistencies of classical defect specifications as applied in the sub-wavelength era. To overcome these issues, the authors propose a new strategy to assess photomask quality by checking the CD variation on wafer (defect printability) using aerial image simulation. This method of simulation-based mask qualification uses aerial image defect simulation in combination with a high resolution optical review system with shorter review wavelength (248nm) and smaller pixel size (22.5nm)- combining the defect inspection system with a longer inspection wavelength (365nm) and larger pixel size (150nm). This paper discusses a new strategy on mask quality assurance with several experimental results that proves the applicability for enabling 90nm technology nodes. Combining high-resolution optical images captured by DUV measurement tool with Virtual Stepper System has achieved better accuracy for 0.72um contact holes on ArF Att.PSM. However, we need further investigation for precise prediction of CD variation caused by defects on 0.4um line/space patterns on ArF Att.PSM. This paper also discusses future work to make the strategy production-worthy.

Increasing complexity, smaller design rule and development of PSM (Phase Shift Mask) are required more precise photomask repair technology. Recently, It is important unit process to enhance yield, production time and delivery in 130nm node below mass production. Furthermore, opaque defects are on the increase compare to clear defects using dry process. Therefore key issue of advanced repair technology is opaque defects removal and edge placement accuracy control. In this paper, we will discuss opaque repair technology of 90nm node EA-PSM to get improved edge placement using FIB (Focused Ion Beam) machine. Firstly, we started with a concept of low ion beam current at 30keV acceleration voltage. To optimize image quality in low beam current, we have changed suitable scan parameters in target FOV (Field Of View) and checked scan damage in these parameters with AIMS. Secondly, we have applied a reregistration function to enhance edge placement control and analyzed edge placement variation by CD-SEM and AIMS tool after pattern drift. Thirdly, transmission of repaired region was confirmed with AIMS and inspection tool.

As advanced photolithography extends the ability to print feature sizes below the 100 nm technology node, various reticle enhancement techniques (RET) are being employed to improve resolution. An example of RET is the alternating phase shift mask (APSM), which currently challenges the ability of conventional repair techniques to repair even the most basic reticle defect. The phase shifting quartz bump is one defect type critical to the performance of APSM technology masks. These defects on the APSM reticle are caused by imperfections in the resist image during processing, resulting in a localized under or over etch of the quartz substrate. The integrated application of gas assisted etch (GAE), focused ion beam (FIB) reticle repair, and atomic force microscopy (AFM), provide a comprehensive solution for advanced reticle defect repair and characterization. Ion beam repair offers superior accuracy and precision for removal without significant damage to the underlying or adjacent quartz. The AFM technique provides quantitative measurement of 3D structures, including those associated with alternating phase shifters etched into quartz as well as embedded shifters. In the work presented in this paper, quartz bum defects were pre-scanned on an AFM tool and proprietary software algorithms were used to generate defect image and height map files for transfer to the FIB reticle repair tool via a network connection. The FIB tool then used these files to control selectively the ion dose during the corresponding quartz defect repair. A 193 nm APSM phase shift photomask with programmed defects in 400 nm line and space pattern was repaired using an FEI Stylus NanoProfilometer (SNP) and a FEI Accura 850 focus ion beam (FIB) tool. Using the APSM FIB repair method, the transmittance evaluated from 193 nm AIMS at the repair area was more than 90% without post-processing.

Photomask is a key factor to support the lithography technology. Defect repairing technology has become more important than ever to keeping the photomasks' integrity in the manufacturing processes. The SIR5000 is a photomask defect repair system for ArF/90 nm generation lithography. In this work, the repaired masks by the SIR5000 were evaluated by an Aerial Imaging Microscope System (AIMS) and Atomic Force Microscope (AFM). These test results do not show actual printing condition on wafer, but rather a simulated lithography image. In this paper, we present the imaging damage, the edge placement repeatability, the repair area's transmission and the printing performance on wafer. An ArF scanner was employed for the tests on the imaging damage and the printing performance. The transmission of imaged area is more than 95% after 70 scanning frames. The edge placement has shown the 90 nm node repair capability. The transmission of repaired area is no issue by AIMS193 analysis. The actual printing result on wafer has shown there is no printing issue. The SIR5000 is well suited for ArF generation lithography.

Nanomachining is a new technique for repairing photomask defects. The advantages of this technique are no substrate damage, precise edge placement position and Z height accuracy when compared with current Laser zapper or FIB GAE repair techniques. This technique can be applied to any type of opaque defects at any type of film materials and quartz bump defects on Alternating Aperture Phase Sifting Masks (AAPSM). Furthermore, these characteristics enable complex pattern repairs of most advanced photomasks for 193nm lithography and enables iterative repair to achieve improved printing performance when analyzed with an AIMS 193nm tool. Dai Nippon Printing Co., Ltd. (DNP) has been producing AAPSMs in mass production for quite some time. The standard type of AAPSMs manufactured has been etched quartz, single trench with an undercut structure. On this structure, there is a potential for quartz defects underneath the chrome overhang based on the combination of dry and wet etching to create the undercut. For this study, we fabricated this kind of designed quartz defects and repaired them using the nanomachining system. These types of defects are particularly difficult to repair perfectly because they exist underneath the chrome overhang. We will show some options to achieve better printing results through the repair of these kinds of defects. In this report, we confirmed basic performance of this technique such as edge placement accuracy, Z height accuracy and AIMS printability. Additionally, we also tried to repair some complex defects such as quartz defects of AAPSM, quartz defects of CPL mask and oversized Serifs for application options. We will show these nanomachining repairs with evaluation results of printing performance simulated by the AIMS 193nm tool.

As lithography wavelengths reduce, the depth of focus decreases rapidly as well, resulting in the need for flatter photomasks with specifications under 0.25 microns. With the introduction of EUV mask technology, the overlay error budget drives the flatness requirements considerably lower to just 50 nanometers or so. This paper describes a new tool that utilizes near normal incidence interferometry to perform flatness measurements on polished 6025 photomasks that are coated or uncoated. Achieving a low measurement uncertainty required a robust optical and mechanical design. Even nanometer level measurement errors due to gravity sag have to be considered. Supporting the substrate during measurement creates deformations due to gravity that must be dealt with for an accurate evaluation of the flatness. Two improvements to the recently introduced Corning Tropel UltraFlat Mask System that first minimize and then remove the remaining gravity sag errors in photomask flatness measurements will also be discussed.

The challenge to achieve an early introduction of 157 nm lithography requires various advanced metrology systems to evaluate the 65 nm node lithography performances, equipments and processes. Carl Zeiss AIMS tool based on the Aerial Image Measurement Software is the most promising approach to evaluate the mask quality in terms of aerial image properties, in order to assess post repair quality. Selete has joint activities with Carl Zeiss, International SEMATECH and Infineon to accelerate the development of an AIMS tool operating at the 157 nm wavelength. The alpha tool phase of the project has been completed, and beta tools are currently being built. This paper is discussing the results from measurements on the alpha tool of some 157 nm attenuated phase shift masks (Att-PSM). Resolution results and CD evaluation with respect to these measurements will be presented.

Mask characterization and qualification are becoming more and more difficult for high-end and alternating phase shifting masks. One choice is to use indirect methods like as SEM/AFM measurements to characterize mask performance. The indirect measurement has the disadvantage that the measured CD is not the true merit function. It is therefore tempting to use optical methods to characterize masks. The Zeiss AIMS (Aerial Image Measurement System) microscope is particular appealing for this task since it simulates the lithographic imaging optics. The key problem is the reliability and repeatability of the resulting AIMS measurements. The quality of the measurement depends strongly on the tool characteristic such as illumination stability and operator skill, e.g. for focus adjustment. In this paper we discuss the application of image processing and Fourier analysis techniques to AIMS images of periodic structures. By computing the Fourier series coefficients one obtains a very compact but complete description of the AIMS image over defocus. This computation and interpretation of the series coefficients allows to compensate many error influences such as mask rotation, tool magnification and focus adjustment. The algorithm is demonstrated on COG and alt. phase shifting mask measurements for a wavelength of 193nm and compared to the results obtained by simulation.

Though phase-shifting interferometry (PSI) is widely regarded as the method of choice for precision measurements of the surface and bulk characteristics of optical components, conventional PSI suffers from severe distortions in the presence of multiple reflections caused from co-parallel surfaces. The optical and physical characteristics of hard pellicles used for 157nm lithography mean that they are essentially parallel plates and the use of standard PSI techniques to evaluate the optical quality of these components will suffer from these problems. We describe a measurement method called Fourier Transform phase-shifting interferometry (FTPSI) that can overcome the disadvantages of standard PSI by the use of wavelength tuning and special analysis techniques. The technique can measure several surfaces simultaneously without distortion from multiple interference effects and is applied to the measurement of mounted and unmounted pellicles. Additionally, bulk properties of the pellicle, such as index homogeneity, can be easily measured with high precision. By spectrally separating the interference produced by different surfaces in the cavity during a wavelength chirp, each surface is identified and measured individually. In this paper, we describe the technique and give examples of measurements of hard pellicles provided by International SEMATECH.

Mask data preparation is a complicated process because many kinds of pattern files and jobdeck files flow into mask manufacturers. This situation has a significant impact on data preparation operations especially in mask manufacturers. In this paper, we propose a solution to this problem: use of unified mask data formats for EB writers and a model of data preparation flow from a device manufacturer to an EB writer. The unified formats consist of pattern data format named "NEO", and mask layout format named "MALY". NEO is a stream format which retains upper compatibility to GDSII and has higher compression rate than GDSII. NEO is intended to be a general input format of Variable-Shaped-Beam (VSB) mask writers in principle, not particularly designed for any specific equipment or software. Data conversion process between mask writers being taken into account, NEO requires some constraints for VSB mask writers, such as removal of overlapping figures. Due to many differences in jobdeck syntax and functions among mask writers, it is a complicated task to edit or modify a jobdeck, and convert it into another format. MALY is a text-based format whose purpose is to standardize mask layout information among mask writers. This unification of mask layout information optimized for EB writers is expected to reduce workload of mask data preparation significantly. Besides the information described in MALY, some other information specific to the target EB writer, such as drawing parameters, has to be prepared separately. This paper illustrates a model of data flow and benefits of using these unified formats. The format and the data flow are effective in reducing data handling cost, providing flexible data handling solution. Applying the handling flow using NEO and MALY would result in reducing the load on mask manufacturers. Moreover, device manufacturers would be freed from the need to specify the mask writer to be used when ordering masks to mask manufacturers.

The ever growing layout complexity and escalating data volumes to be handled in high-end mask making processes using variable-shaped beam writers (VSB) require totally new computing and software solutions for data preparation. The high-performance, cost-effective LINUX Cluster is the ideal tool to manage these challenging tasks and, in addition, offers the advantage of being upgradable and expandable for meeting future lithography requirements. In this paper different computer configurations are analyzed. As a logical consequence the data conversion issue, including Proximity Effect Correction, of VSB e-beam systems and their specific data formats are also reflected in this investigation. Distributed and multi-threading computing is compared highlighting the advantages of the distributed approach.

An effective algorithm was developed to prepare a mask layout from several chip databases. The underlying idea is solving so called “strip packing” problems, which actually have been very common in many industries. A major difference between applications is the definition of cost function used in a particular packing problem. In the present case, the work is to test whether all component chips can fit onto a mask with limited area and how these chips are placed. Based upon this goal, the cost function is simply the minimum rectangle that can accommodate all chips. If the minimum enclosing rectangle is smaller than the available mask area, it is feasible to make up the desired mask. The algorithm also tells us the placement of all chips if the placement is possible. The computing time is very short, in the range of seconds, and expected to be short for most cases, too. After all, the changes in other cases are the number and sizes of rectangles. For an operation on GDSII files, the required process time is virtually the time of reading component databases and writing out the result database. This is a generic algorithm, so it does not reply on any particular tools. As long as a tool can perform common arithmetic operations and layout generation, it could be used to implement the job. This work eliminates the manual try-and-error packing process during the data preparation stage of a shuttle mask. Breaking one more bottleneck, which is the manual packing process, could significantly reduce the cycle time of mask data preparation.

Following Moore's Law semiconductor industry is going through a challenging transition from 180 nm to 130 nm manufacturing process geometries and rapidly approaching 90 nm geometries. The major challenges associated with the transition to nanometer design include: (1) Increasing design sizes and complexity (e.g. 300-400M transistors for FPGAs); (2) Increasing number of design rules (approaching 2000 for advanced 90 nm processes); (3) Increasing design cycle (4-9 months for ASICs); (4) Increasing design cost (advanced design flow cost $15M+). With the size and complexity of today's advanced ASICs and SoCs, the ability of designers to efficiently fix DRC errors is becoming a critical challenge impacting productivity and time-to-market. Designers need new EDA tools to process designs of very high complexity in shorter time. New tools should bridge design and process worlds by transparently providing designers with more detailed process (lithography) information. In this paper the authors will describe a method for manufacturing verification of automated design rule fixes. Many types of design rule violation are detected, automatically fixed, and verified by lithography simulation.

In recent low-k₁ lithography, OPC is required to generate more aggressively fragmented patterns to keep its pattern fidelity on the LSI devices. But over-aggressive OPC might induce a crisis of mask manufacturability. In this paper, using newly defined parameter, DPF (Degree of Pattern Fidelity), quantitative relations between OPC aggressiveness and pattern fidelity are evaluated under several conditions. Next, the concept of MEF is extended for 2D complex patterns using DPF, and is evaluated as a function of OPC aggressiveness. Other mask manufacturability, such as writing time, data volume, and inspection availability would be evaluated as a function of OPC aggressiveness.

Lithography process modeling is critical for effective model-based optical proximity correction (OPC) or verification. Physics based full resist and etching model can provide very accurate prediction of the resist profile, but its speed forbids the use in practical production OPC and verification applications. Simplified models have therefore been developed. These models collapse some complicated but less crucial physics into "parameters" which are tuned to best fit the real measurement data. However, as the feature patterns vary, the aerial image around the patterns can experience a wide range of intensity distribution patterns. It is difficult to use a single set of "parameters" to fit into all these profiles. As compromises are made, accuracy suffers. The properties that contribute to such variations are primarily pattern shapes, dimensions, and in the case of phase-shift masks, phase-interaction. One way to improve the model accuracy is to build multiple "local" models such that each model contains a set of parameters that are optimized for the given pattern. As we perform simulation, we identify the pattern and then pick the model that is best suited for the given pattern. In this paper, we demonstrate how it is difficult for a single model to fit a set of data with large varying patterns. Then we show how multiple model methodology can be applied to improve model accuracy. As we apply the models, there will be "gray" areas where the pattern is not clearly identified to belong to the class for which a model is available. We explain how such situation should be coped with, and how the simulation responds to model "switching".

Conventional simulation tools that verify the layout of a subwavelength IC against the silicon it is intended to produce. It reads in the layout and simulates lithographic process effects, including optical, resist and etch effects. Then compares the results -- the simulated "silicon image" -- with the original (intended) layout, reporting out-of-tolerance regions. We here introduce a reverse engineering method that use ready database to simulate unknown pattern. By using this method, you can get more fast and accurate results then conventional simulation tools. We will discuss the advantage and disadvantage of this method and its application.

It depends for the writing time of variable shaped electron-beam (VSB) writing system on the number of writing shots. For shortening of writing time, it is most effective to reduce the number of shots. However, Resolution Enhancement Technologies (RET), such as OPC and PSM, make the VSB shot number increase explosively, in addition to reduction of LSI pattern size, and worsens the writing throughput. This is a serious problem for VSB mask writer, and the improvement of a writing throughput is required. In order to solve this problem, we inquired towards diversifying beam shape only from a rectangle. First, we investigated about the curtailment effect of the number of shots by trapezoid aperture adoption. Some latest VSB writer has adopted a triangle shaped aperture to compose the slanting figure in the LSI pattern efficiently. We investigated the efficiency of forming the slanting figure with trapezoid or parallelogram apertures compared with initial triangle aperture shot number. As the result of that, shown in Fig.1, we obtained the result that the shots number was reduced into 50% or more compared with initial triangle shots number. And, we examined a possibility of uniting and applying the character projection (CP) technique, which is adopted as EB direct writing (DW), to mask writing. Since pattern size is, for example, 4 times larger in the case of mask writing compared with the case of EBDW, the area that can extract a common CP pattern out from LSI patterns at mask writing is smaller than EBDW. Then, we extracted CP aperture pattern from cell library data for logic LSI. We obtained the result, shown in Fig.2, that the shot number that was used CP aperture was reduced into about 35% compared with initial VSB shots number. However, the arrangement number of aperture has restriction, and if the arrangement number decreases, the curtailment rate of the shots number will fall. These two techniques are fundamentally effective in curtailment of writing shots number. Furthermore, we will discuss with the possibility of applying these techniques to mask writing and with some problems to solve for the application of these techniques.

The introduction of photomask laser pattern generators presents new challenges to system designers and manufacturers. One of the laser pattern generator's environmental operating challenges is Airborne Molecular Contamination (AMC), which affects both chemically amplified resists (CAResist) and laser optics. Similar challenges in CAResist protection have already been addressed in semiconductor wafer lithography with reasonable solutions and experience gained by all those involved. However, photomask and photomask equipment manufacturers have not previously had a comparable experience, and some photomask AMC issues differ from those seen in semiconductor wafer lithography. Culminating years of AMC experience, the authors discuss specific requirements of Photomask AMC. Air sampling and material of construction analysis were performed to understand these particular AMC challenges and used to develop an appropriate filtration specification for different classes of contaminates. The authors portray the importance of cooperation between tool designers and AMC experts early in the design stage to assure goal attainment to maximize both process stability and machine productivity in advanced mask making. In conclusion, the authors provide valuable recommendations to both laser tool users and other equipment manufacturers.

A new advanced electron beam lithography system JBX-3030MV has been developed to meet requirements for the production of masks for 100-90nm technology node. The system features a variable shaped beam, 50kV accelerating voltage, a step-and-repeat stage, and incorporates new technologies. These include a high resolution-high current density electron optical system, triangle beam shaping system, higher speed electro static beam deflection system, higher accuracy proximity effect correction system, and glass in glass out material handling system. The writing accuracy of the system has satisfied the specifications required for the production of 100-90nm node reticles with extendibility of 65nm node reticles.

Evaluation of the patterning accuracy of e-beam lithography machines requires a high precision inspection system that is capable of measuring the true xy-locations of fiducial marks generated by the e-beam machine under test. Fiducial marks are fabricated on a single photo mask over the entire working area in the form of equally spaced two-dimensional grids. In performing the evaluation, the principles of self-calibration enable to determine the deviations of fiducial marks from their nominal xy-locations precisely, not being affected by the motion errors of the inspection system itself. It is, however, the fact that only repeatable motion errors can be eliminated, while random motion errors encountered in probing the locations of fiducial marks are not removed. Even worse, a random error occurring from the measurement of a single mark propagates and affects in determining locations of other marks, which phenomenon in fact limits the ultimate calibration accuracy of e-beam machines. In this paper, we describe an uncertainty analysis that has been made to investigate how random errors affect the final result of self-calibration of e-beam machines when one uses an optical inspection system equipped with high-resolution microscope objectives and a precision xy-stages. The guide of uncertainty analysis recommended by the International Organization for Standardization is faithfully followed along with necessary sensitivity analysis. The uncertainty analysis reveals that among the dominant components of the patterning accuracy of e-beam lithography, the rotationally symmetrical component is most significantly affected by random errors, whose propagation becomes more severe in a cascading manner as the number of fiducial marks increases.

We describe a newly developed technique that uses optical projection lithography with a liquid crystal display (LCD) in place of a conventional reticle, in order to minimize turn-around-time and production cost. Circuit pattern data, generated by a computer aided design (CAD) system, is transferred directly to a control computer. The control computer converts the data into an equivalent dot matrix representation of the design for use on a LCD. The LCD is placed in a conventional optical stepper. One feature of this system is the simplicity of the data management scheme which permits the data to be handled by a computer file directly; without any of the manual assistance normally needed in conventional reticle fabrication. It is a very convenient method to reverse reticle tone by changing the LCD mode; easy compared to a conventional reticle manufacturing process. The minimum resolution of this proposed system is very similar to conventional systems that use optical reticles. We have demonstrated that this LCD Reticle-Free Exposure Method has the potential of replacing conventional reticles in optical stepper lithography. This method is applicable for manufacturing devices with relatively large fabrication rules and low production quantities, such as System-in-Package applications.

Photomask resist strip processes have traditionally used the sulfuric-peroxide-mix, known as SPM, or Piranha. This paper details a recent investigation into the utilization of solvent-based resist strip solutions applied to photomask resist stripping. Studies of two commercially available solvents are documented in this report: one formulated for positive resist stripping [Chem A, which contains a primary amine, glycol and is semi-aqueous], and another rated for 'hard-to-remove' positive resist stripping [Chem B, which contains glycol ethers, organic cyclics -- all proprietary]. Resist types, such as IP3600, and most Chemically Amplified Resists (CAR) will strip easily with any of the chemicals mentioned, however, other adverse effects may deter one from using them. The screening process employed in this study monitors effects of processing on EAPSM phase and transmission, AR layer reflectivity changes and surface ionic analytical comparisons. Chem A and B will show similarly low phase and transmission shifts at higher temperature and longer process times, while reflectivity data shows lower level changes associated with the use of Chem A (favorable). As for surface ionic contamination: on F and Cl contaminated surfaces, Chem A shows favorable results. Overall Chem A seems to be the appropriate choice for more thorough investigation in a production mask-making environment.

Because 157 nm light energy is two or more times of C-C bonding energy, the main bonding of organic materials, pellicle membrane material decomposes if it absorbs light at 157 nm. Therefore, in order to ensure the durability of the pellicle membrane, it is very important that the membrane material absorbs 157 nm light as little as possible. We researched high transmittance polymers at 157 nm by using simulation technology. In conclusion, we estimated that polymers with high transmittance at 157 nm are possible, and several companies were asked to develop it. As a result, we obtained a polymer in which 157 nm transmittance is 98.5% at 0.8 um [157 nm absorbance is 0.008 um^-1, 10 base] from Asahi Glass Co., Ltd. We carried out various 157 nm irradiation tests by using the above polymer, and obtained the result showing durability of 15 J/cm² in nitrogen + 1000 ppm oxygen environment. Furthermore, we examined the environment during F₂ Excimer Laser irradiation and found that transmittance loss of membrane and also oxygen addition quantity to irradiation environment may be improved substantially by adopting irradiation environment of Helium.

At Intel Mask Operations (IMO), Standard Mechanical Interface (SMIF) processing has been employed to reduce environmental particle contamination from manual handling-related activities. SMIF handling entailed the utilization of automated robotic transfers of photoblanks/reticles between SMIF pods, whereas conventional handling utilized manual pick transfers of masks between SMIF pods with intermediate storage in Toppan compacts. The SMIF-enabling units in IMO's process line included: (1) coater, (2) exposure, (3) developer, (4) dry etcher, and (5) inspection. Each unit is equipped with automated I/O port, environmentally enclosed processing chamber, and SMIF pods. Yield metrics were utilized to demonstrate the effectiveness and advantages of SMIF processing compared to manual processing. The areas focused in this paper were blank resist coating, binary front-end reticle processing and 2nd level PSM reticle processing. Results obtained from the investigation showed yield improvements in these areas.

A new methodology for a mask quality, flexible mask specifications, is proposed. This methodology consists of two major concepts. One is a flexibly selected pattern to guarantee a mask quality for each device and each level of a device. This pattern, hot spot pattern, is selected using a full chip level lithography simulation. The other is flexibly changeable combination of each tolerance of each error component (e.g. CD mean to target, CD uniformity). A mask quality is judged by not each error component, but a total lithography margin. In this methodology, following two points are important. A hot spot pattern should be correctly selected in terms of having large impact on critical dimension (CD) on wafers. An amount of lithography margin reduction due to mask manufacturing error should be correctly estimated. We have improved this methodology in those two points. Firstly, a hot spot pattern is selected in terms of difference of Dose-MEF factor in addition to a pattern having small lithography margin. A Dose-MEF factor defines as ratio of target exposure shift to mask CD error. A difference of Dose-MEF reduces a common lithography margin with patterns having CD errors. Secondary, we measure all kinds of hot spot patterns directly. A common lithography margin is obtained from Exposure-defocus tree (ED-tree) based on actual measurement data. Applying these improved methodologies to memory device mask with 130nm node, we can obtain a lithography margin precisely in comparison with the previous method.

For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.

Design and optical proximity correction (OPC) flow with hybrid OPC and manufacturability check (MC) tool was found to be effective for making robust pattern formation without any hot spots within feasible lead time under the low-k1 lithography condition. MC at design stage is essential for cleaning up hot spots in three ways; the refinement of design rule, the guideline for repairing hot spots for designers and the refinement of OPC deck. Hybrid OPC and MC tools with library- and model-based modules are available for reducing lead time by taking advantage of library system. Due to the design and OPC flow with the library-based OPC and MC tool, total lead time can be reduced to 55% of that in the case of conventional flow with MC. Assuming that a refined mask is ordered due to issue of hot spots without MC, the total lead time in the new flow can be reduced to 11% of that in the case of conventional technology.

Recently as the node size gets smaller into deep sub-micron, both chip designers and mask manufacturers have faced great problems as follows: (1) Explosion of the data size; (2) Further data complexity due to OPC or PSM; (3) Increasing numbers of data formats. Since these problems directly lead to the increase of the mask costs, we have thought that they need to be overcome from the viewpoint of data processing as well. Selete have made a proposal of a next generation EB handling format, called 'NEO', in order to cope with these issues. The greatest feature of NEO is its compaction capability of the data description and it is expected that the chip data size could be reduced far smaller than in any other existing EB formats. We have been working on the NEO project in cooperation with Selete and developed a new system 'GDS2NEO', which converts the conventional layout data described in GDSII to the NEO-formatted data. We also investigated the compaction efficiency of NEO with several sets of actual layout data using GDS2NEO. As the result, we have proved that NEO has an excellent efficiency of data compaction and GDS2NEO has achieved a satisfactory performance of data conversion. In this paper we present the concept of NEO format, the data processing flow and the basic algorithm of GDS2NEO, the experimental results and the future plans.

Mask manufacturing for the 100 and 65nm nodes is accompanied by an increasing deployment of VSB mask writing machines. The continuous integration trend in design and broad deployment of RET have a tremendous impact on file size and pattern complexity. The impact on the total turn-around time for a design is twofold: the time to get the data ready for the hand-off to the mask writer is growing but also the time it actually takes to write the mask is heavily influenced by the size and complexity of the data. Different parameters are measures of how the flow and the particular tooling impact both portions. The efficiency of the data conversion flow conducted by a software tool can be measured by the output file size, the scalability of the computing during parallel processing on multiple processors and the total cpu-time for the transformation. The mask writing of a particular data set is affected by the file size and the shot count. The latter one is the total amount of shots that are required to expose all patterns on the mask. The shot count can be estimated based on the figure count by type and their dimensions. The results of the fracturing have an impact on the mask quality -- in particular the grid size and the number and locations of small figures.

HL-7000M electron beam lithography system has been developed as a state-of-the-art reticle writer for the generation of 90nm node production and 65nm node development. It is capable of handling relatively large volume data files such as full Optical Proximity Correction patterns and angled patterns for System on Chip. Aiming at technological requirements, a newly designed electron optics column generating a vector-scan variable shaped beam and a digital disposition system with a storage area network technology have been integrated into HL-7000M. Since the requirement on the critical dimension uniformity is extremely demanding on the ITRS roadmap, HL-7000M has also needed to improve its beam shaping performance. The ability relevant to shaping beam size has a great impact on its line width or critical dimension accuracy. To reduce an aberration caused within the shaping lens system, the dual quadrupole electrostatic shaping deflector has been utilized. By applying advanced technologies, HL-7000M with a result of critical dimension uniformity (2.5nm and 2.8nm in 3σ) has achieved meeting its target requirement of the 90nm generation for production. Additionally HL-7000M has proved its potential, allowing the industry to establish quickly the processes further beyond the requirements of the 65nm node for development.

Mask cost is a key challenge for the semiconductor industry and a major issue is the write times of e-beam pattern generators. DUV pattern generators can provide high throughput, but there is a cost and time involved in qualifying these tools for IC production. To minimize this time and cost, the masks from the DUV tool should have pattern fidelity similar to that of e-beam tools. This can be done with corner enhancements on an imaging DUV mask writer. Here, we describe such a corner enhancement scheme and present results for the 65-nm-node requirements. We demonstrate how the corner radius can be tuned in a range of radii with a negligible effect on the process latitude.

Haze is a kind of surface contamination on photomask and lithography optics that made by photochemical reaction. There are many problems in photomask manufacturing, inspection and lithography process because of slowly growing feature of haze. In the photolithography process, the wafer damage has been occurred due to the time dependent growth of haze. In this study, we identified the origin and formation mechanism of haze using accelerated contamination experiments, also developed control method for haze, in which the removal efficiency was confirmed by mass production of photomask. From these results we expect that the photocontamination control technology should be developed and been an important part of NGL technology.

To improve the first pass defect level in a process, the implementation of a full Standard Machine Interface (SMIF) material handling system in first-level front end processes is a very effective method, due to the reduction of handling and clean-room particles on masks. The justification of such an investment into SMIF equipment is the corresponding increase in yield. Verification of this yield increase was done with data from Infineon maskhouse. Since the implementation was performed stepwise, a detailed defect data analysis had to be done. The total observed defect related yield enhancement SMIF implementation phase of approximately one year for the first level, was in the range of ~ 20%. To distinguish SMIF related improvements from other defect yield improvements during this time, the overall defect related yield was broken down into single process yields. The single process yield enhancements were calculated only with defects originating from particles at these process steps. The particle performance of SMIF pods was tested since the masks are put in the pods with chrome side up. Compared to conventional box types the particle adders due to pod handling on the masks in the SMIF pods was very low.

Effects of mask CD error on lithography performance are estimated as the metric “dose-MEF”. The mask CD error is classified into three categories in accordance with the spatial frequency (global, local and LER). In the global CD error, the CD is constant within the range where the OPE reaches. The local CD error has the spatial frequency that is nearly equal to OPE range. The LER has very small spatial frequency by comparison with OPE range. The effects of local CD error and LER are estimated by using Monte Carlo Simulation because of randomness. For dense pattern, dose-MEF for local error is half of that for global error. Further, dose-MEF for LER is so small that this effect is negligible. Therefore, specifications for mask CD error must be decided by considering dose-MEF for each category.

Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell and logic patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 90 nm node DRAM and logic layers concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. We also introduced concept of checkerboard CLM to apply zigzag L/S and semi dense contact in the logic layer. Using 0.75 NA ArF Scanner, CLM showed NILS reduction by 10~15% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2 μm depending on the layer. So the critical layers in sub 90 nm node DRAM satisfied 8% of EL (Exposure Latitude) and 0.3 μm of DoF (Depth of Focus) margin. Also 3D mask topographic effect of CLM in the specific contact layer was discussed.

The TaSiOx attenuated phase-shifting mask (Att-PSM) has strong potential for durability against laser irradiation and good lithographic performance in 157 nm lithography. However, the resist resolution limit and depth of focus (DOF) are deteriorated by side-lobe patterns generated near the contact hole. This is because the side-lobe intensity generated near the light-transmitting region becomes larger in sub 100 nm contact holes. To minimize the effect of side-lobes and improve lithographic performance, we evaluated an Att-PSM with a chrome light-shielding layer and optimized the transmittance of its attenuated phase-shifting film. In an optical simulation, we investigated the effect of the side-lobe intensity on the resist region (i.e., a reduction in resist thickness). The light-shielding film was placed on the attenuated phase-shifting film to prevent the side-lobe pattern, and its effect on the imaginary resist pattern was simulated. We found that the distance between the patterning edge of the hole and that of the light-shielding region must be greater than 90 nm to fabricate a 100 nm isolated hole without side-lobe patterns. The side-lobe intensity could be controlled using the chrome-shielding-type Att-PSM, and the lithographic performance (such as resolution limit and DOF) was enhanced.

A comprehensive study of alternating phase shifting mask (Alt-PSM) including mask making, 3-dimensional aerial image simulation, and wafer printing is reported in this paper. For the mask making, we found that the micro-loading effect will be greatly improved using the etching recipe with high Reactive Ion Etching (RIE) power and low Inductively Coupled Plasma (ICP) power. However, this recipe has side effects of Cr film damage and rough quartz side wall. Due to the 3-dimensional mask complex effect, the optimal phase difference is not simply π calculated using optical path difference but is varied with mask features. The optimal phase difference is 165° other than 180° for hole patterns, while it is 176° for line-and-space patterns. The micro-loading effect with variant 2-dimensional complexities is also studied in this paper.

The impact of phase defect printability on a wafer in alternating phase shift masks (alt-PSM) was investigated. The Alt-PSM is a promising resolution-enhancement technique for extending optical lithography to a finer design rule. One of the important issues in the practical use of alt-PSMs is the realization of defect-free mask manufacturing. In order to investigate the effect of phase defects on wafer printability, CD error on a wafer was evaluated using ArF exposure experiments and 3D simulations. The alt-PSM of a single-trench structure with undercut was selected. In comparison of exposure and simulation results, it is shown that the necessity for taking phase defect topography into consideration strictly in 3D simulation. From the results of the optimized simulations, allowable defect sizes of bump center and edge were 55 and 85 nm, where the phase difference was 180 degrees. The defect size of divot center and edge were 200 and 100 nm, where the phase difference was 180 degrees. Also, the present inspection sensitivities of phase defects is checked by the critical defect sizes of alt-PSM.

The complexity of Resolution Enhancements Techniques (RET) will increase dramatically in the next four generations of optical lithography, requiring careful qualification of new reticle designs when they arrive at the wafer fab and before commiting them to printing product. Low k₁ and high MEF lithography increase the printability and frequency of yield impacting repeating defects from reticle defects and RET layout errors. Therefore, reticle qualification must include qualifying the reticles for mask processing errors as well as for RET design rule violations. The former is performed on a reticle inspection tool and the latter on a wafer inspection tool after printing wafers with a specific layout using the reticles of interest. The output from the wafer inspection tool followed by detailed analysis provides information on the regions of marginality within the reticle field or features within the die which have smaller process window than expected. We call this the Process Window Qualification Output, PWQ Output and it can be applied to single and multi-die reticle designs. Once these locations are identified by PWQ and the features are determined to be critical to the functionality of the device, further process window analysis on the CD SEM is performed to identify if sufficient process window overlap exists between these features and all other critical features in the device. If the process window overlap of the marginal features with other critical features is acceptable, the reticle can be used to print product. These marginal regions are then carefully monitored on product by CD Metrology. If insufficient overlap in the process windows is found, the PWQ Output features are overlayed with the CAD design and a design fix might be required, followed by the manufacturing of a new reticle. In this paper we describe how we used the PWQ methodology to identify RET design errors for three different reticle designs; in the first example, the marginal feature is an OPC sizing error causing the below design rule spacing in a 0.13μm Gate reticle design to bridge within the process window and the second example is that of a marginal feature associated with improper biasing and a phase error for an Attenuated PSM reticle. The final example shows how PWQ was used to verify the printing of an assist feature within the process window for a Gate 0.13μm reticle.

In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRS's roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation, the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.

Using TEM copper grid with different pitch size as physical mask, alkanethiolates self-assembled monolayers was patterned by a metastable helium atom beam, demonstrating pattern transfer with nanoscale edge width to the underlying gold film. We found that the mask was reproduced as positive- or negative patterns with high fidelity, and the repetition of lithographic patterns was good in different runs.

In high-voltage electron beam lithography, most of the beam energy is released as heat and accumulates in the local area of writing. Excessive heat causes changes in resist sensitivity, which in turn causes significant critical dimension (CD) variation. Previous methods for reducing CD distortion caused by resist heating include usage of lower beam currents, increased delays between electron flashes, and multi-pass writing. However, all these methods lower mask writing throughput. This leads to increased mask writing cost, which is increasingly becoming a major limiting factor to semiconductor industry productivity. In this paper, we propose a new method for minimizing CD distortion caused by resist heating. Our method performs simultaneous optimization of beam current density and subfield writing order. Simulation experiments show that, compared to previous methods, the new subfield scheduling method leads to significant reductions in resist temperature with unchanged mask writing throughput. Alternatively, subfield scheduling can be coupled with the use of higher beam current densities, leading to increased writing throughput without increasing CD distortion.