A methodology to analyze circuit impact of process-related MOSFET geometry

Artur Balasinski

doi:10.1117/12.532860

3 May 2004 A methodology to analyze circuit impact of process-related MOSFET geometry

Artur Balasinski

Author Affiliations +

Proceedings Volume 5379, Design and Process Integration for Microelectronic Manufacturing II; (2004) https://doi.org/10.1117/12.532860
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

Deep sub-wavelength optical imaging distorts the shape of MOSFET channel on silicon due to proximity and refraction. As a result, channel area is no longer rectangular, i.e., represented by the single channel length and width (LxW) for device simulations, but by an L(W) distribution. This distribution would differ across the optical proximity correction (OPC) and photo process windows, possibly exceeding the typical 10% CD variation entitlement. While one can expect that the process-related L(W) would impact MOSFET electrical properties, its circuit consequences have not been addressed in the typical simulation flow. In this work, we examine the impact of non-rectangular channel geometry on the basic MOSFET parameters such as the drive and leakage current. We then create models of the resulting inverter characteristics and of the static noise margin of an SRAM cell. In the process, we show how to simulate MOSFET gate shape for the different OPC and lithography options and identify the channel sections responsible for the parametric variations. Finally, we calculate electrical characteristics of SRAM cell based on the discretized representation of individual MOSFETs, showing how the distortion of channel geometry would degrade cell performance.

Citation Download Citation

Artur Balasinski "A methodology to analyze circuit impact of process-related MOSFET geometry", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); https://doi.org/10.1117/12.532860

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