FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

Krzysztof T. Pozniak

doi:10.1117/12.568878

22 July 2004 FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

Krzysztof T. Pozniak

Author Affiliations +

Proceedings Volume 5484, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments II; (2004) https://doi.org/10.1117/12.568878
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments II, 2003, Wilga, Poland

Abstract

The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY). A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

Citation Download Citation

Krzysztof T. Pozniak "FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments", Proc. SPIE 5484, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments II, (22 July 2004); https://doi.org/10.1117/12.568878

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