High bit rate BPSK receiver

J. A. Osorio-Marti; J. J. Sieiro; J. M. Lopez-Villegas

doi:10.1117/12.608385

30 June 2005 High bit rate BPSK receiver

J. A. Osorio-Marti, J. J. Sieiro, J. M. Lopez-Villegas

Author Affiliations +

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608385
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

This work presents a simple differentially BPSK receiver front-end using a novel schema without the need of an explicit carrier recovery system. The main principle of operation is the conversion of the incoming BPSK signal into an ASK signal having the same modulation pattern. Two versions of the system have been designed. One is intended to work at the 433.92 MHz ISM band and the other at 2 GHz frequency band. Accordingly, two prototypes of the system core, the BPSK to ASK converter circuit, have been implemented and tested. First a hybrid version for the low frequency operation and, second a multi chip module (MCM) for the 2 GHz frequency band. The system performance has been evaluated using Agilent Technologies Advanced Design System (ADS) platform. The ability to jointly perform system, circuit and EM simulations and co-simulations is the main advantage of this design tool. Obtained results indicate that modulation rates up to 20 Mbits/s for the hybrid version and up to 80 Mbits/s for the MCM version can be reached.

Citation Download Citation

J. A. Osorio-Marti, J. J. Sieiro, and J. M. Lopez-Villegas "High bit rate BPSK receiver", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608385

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