Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of equipment for mask fabrication. This year's assessment is the fourth in the current series of annual reports and is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the mask industry. This report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results may be used to guide future investments on critical path issues. This year's survey contains all of the 2004 survey questions to provide an ongoing database. Additional questions were added to the survey covering operating cost factors and equipment utilization. Questions are grouped into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery times, returns and services, operating cost factors and equipment utilization. Within each category are a many questions that create a detailed profile of both the business and technical status of the mask industry. This assessment includes inputs from eight major global merchant and captive mask manufacturers whose revenue represents approximately 85% of the global mask market. This participation rate is reduced by one captive from 2004. Note: Toppan, DuPont Photomasks Inc and AMTC (new) were consolidated into one input therefore the 2004 and 2005 surveys are basically equivalent.

RET (Resolution Enhancement Technique) is strongly required for 65nm node pattern generation. Alternating Phase Shift Masks (APSM) and Chrome-less Phase Lithography (CPL) masks are widely used for the purpose of RET. However, APSM and CPL mask manufacturing is rather complex and difficult in terms of their structure and fabrication. To inspect these kind of RET masks is very difficult because of quartz (Qz) phase defects which can hardly be detected by using a conventional inspection method. Since Qz phase defect is the key issue in APSM or CPL mask manufacturing, many works have been done widely so far. Here we've evaluated the defocus inspection method to find best inspection condition for detecting Qz phase defects. We conclude that the best condition for finding Qz phase defects could have dependency upon the pattern shape and size. Moreover, the limitation of the inspection capability for Qz phase defect inspection has been addressed with comparison of the wafer print result.

Progressive mask defect problem is an industry wide mask reliability issue. During the start of this problem when the defects on masks are just forming and are still non-critical, it is possible to continue to run such a problem mask in production with relatively low risk of yield impact. But when the defects approach more critical state, a decision needs to be made whether to pull the mask out of production to send for clean (repair). As this problem increases on the high-end masks running DUV lithography where masks are expensive, it is in the interest of the fab to sustain these problem masks in production as long as possible and take these out of production only when absolutely necessary; i.e., when the defects have reached such a critical condition on these masks that it will impact the process window. During the course of this technical work, investigation has been done towards understanding the impact of such small progressive defects on process window. It was seen that a small growing defect may not print at the best focus exposure condition, but it can still influence the process window and can shrink it significantly. With the help of a high-resolution direct reticle inspection, early detection of these defects is possible, but fabs are still searching for a way to disposition (make a go / no-go decision) on these defective masks. But it is not an easy task as the impact of these defects will depend on not only their size, but also on their transmission and MEEF. A lithographic detector has been evaluated to see if this can predict the criticality of such progressive mask defects.

The standard inspection flow typically consists of transmitted light pattern inspection (die-to-die or die-to-database) and STARlight^TM (Simultaneous Transmitted And Reflective Light) contamination inspection. The initial introduction of TeraScan (DUV) inspection system was limited to transmitted pattern inspection modes. Hence, complete inspections of critical mask layers required utilizing TeraScan for maximized pattern defect sensitivity and the previous generation TeraStar (UV) for STARlight^TM contamination inspection. Recently, the reflective light die-to-database (dbR) inspection mode was introduced on the DUV tool to compliment transmitted light die-to-database (dbT) inspection. The dbR inspection mode provides not only pattern inspection but also contamination inspection capabilities. The intent of this evaluation is to characterize the dbR inspection capability on pattern defects and contaminations. A series of standard programmed defect test plates will be used to evaluate pattern inspection capability and a PSL test plate will be used to determine the contamination performance. Inspection results will be compared to the current inspection process of record (dbT + STARlight^TM). Lastly, the learning will be used to develop and implement an optimal dbR inspection flow for selected critical layers of the 65-nm node to meet the inspection criteria and minimize the cycle time.

Semiconductor product designs are necessarily constrained by both the wafer and mask lithographic capabilities. When mask image sizes approach the exposure wavelength, optical and resist effects distort the printed images. Applying optical proximity correction (OPC) to design features on the mask compensates for diffraction effects. However, aggressive OPC introduces even smaller minimum features, adds notches and bulges, introduces sub-resolution assist features (SRAFs) and generally creates a more challenging mask design with respect to data handling, printing and inspection. Mask defect inspection is a critical part of the mask process, ensuring that the mask pattern matches the intended design. However, the inspection itself imposes constraints on mask patterns that can be inspected with high defect sensitivity but low nuisance defect counts. These additional restrictions are undesirable since they can reduce the effectiveness of the OPC. IBM and KLA-Tencor have developed a test mask methodology to investigate the inspectability limits of the 576 and 516 mask inspection systems. The test mask design contains a variety of rules or features that currently impose inspectability limits on the inspection tools, in a range of sizes. The design also incorporates many features essential for obtaining valid results, such as a user-friendly layout, multiple pattern orientations, and background patterns. The mask was built and inspected in IBM Burlington's mask house. Preliminary inspection results will be presented; they underscore the importance of understanding both the inspection tool and the mask process when restricting mask design rules.

As the design rule continues to shrink towards 65nm size and beyond the defect criteria are becoming ever more challenging. Pattern fidelity and reticle defects that were once considered as insignificant or nuisance are now becoming significant yield impacting defects. The intent of this study is to utilize the new generation DUV system to compare Die-to-Die Reflected Light inspection and Die-to-Die Transmitted Light Inspection to increase defect detection for optimization of the 65nm node process. In addition, the ReviewSmart will be implemented to help categorically identify systematic tool and process variations and thus allowing user to expedite the learning process to develop a production worthy 65nm node mask process. The learning will be applied to Samsung's pattern inspection strategy, complementing Transmitted Light Inspection, on critical layers of 65 nm node to gain ability to find defects that adversely affect process window.

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

As the lithography design rule of IC manufacturing continues to migrate toward more advanced technology nodes, the mask error enhancement factor (MEEF) increases and necessitates the use of aggressive OPC features. These aggressive OPC features pose challenges to reticle inspection due to high false detection, which is time-consuming for defect classification and impacts the throughput of mask manufacturing. Moreover, higher MEEF leads to stricter mask defect capture criteria so that new generation reticle inspection tool is equipped with better detection capability. Hence, mask process induced defects, which were once undetectable, are now detected and results in the increase of total defect count. Therefore, how to review and characterize reticle defects efficiently is becoming more significant. A new defect review system called ReviewSmart has been developed based on the concept of defect grouping disposition. The review system intelligently bins repeating or similar defects into defect groups and thus allows operators to review massive defects more efficiently. Compared to the conventional defect review method, ReviewSmart not only reduces defect classification time and human judgment error, but also eliminates desensitization that is formerly inevitable. In this study, we attempt to explore the most efficient use of ReviewSmart by evaluating various defect binning conditions. The optimal binning conditions are obtained and have been verified for fidelity qualification through inspection reports (IRs) of production masks. The experiment results help to achieve the best defect classification efficiency when using ReviewSmart in the mask manufacturing and development.

Silicon Technology Development for the ITRS 65nm-node is in the final stage of an intense 2-year cycle with the full-entitlement technology qualification by the end of 2005. Accordingly, reticle technology development in support of the 65nm-node has advanced a great deal since the initial efforts began several years ago. One of the most challenging aspects of 65nm-node mask technology development is the mask inspection, which is also the main cost-driver for the 65nm-node reticle technology. As a result, controlling 65nm-node reticle cost via leveraging advanced mask inspection technologies has become a leading factor in enabling prolonged success of the 65-nm node technology for years to come. With this paper, we report our closing work on reticle inspection capability development for the 65nm-node process technology development cycle for a full-volume production ramp.

Time-to-mask (ttm) has been growing exponentially in the subwavelength era with the increased application of advanced RET's (Resolution Enhancement Technology). Not only are a greater number of design/mask layers impacted but more-and-more layers also have more severe restrictions on critical dimension uniformity (CDU) despite operating at a very low k₁ factors necessitating rigorous but practical tolerancing. Furthermore, designs are also more complex, may be built up from blocks spanning different design styles, and occupy increasingly-large Rayleigh field areas. Given these factors and scales, it's no wonder that the cycle time for verification of a design following RET, is growing however it is doing so exponentially and that this is a critical factor impeding ttm. Until an unambiguously interprable and standard Mask Design Rule (MaskDR) set is created, neither the designer nor the mask supplier can reliably verify manufacturability of the mask for the simple reason that ambiguity and inter-rule conflict are at the source of the problem and that the problem increasingly requires cooperation spanning a large ecosystem of tool, IP, and mask suppliers all needing to essentially speak the same language. Since the 130 nm node, Texas Instruments has enforced a strict set of mask rule checks (MRCs) in their mask data preparation (MDP) flow based on MaskDRs negotiated with their mask suppliers. The purpose of this effort has been to provide an a-priori guarantee that the data shipped to the mask shop can be used to manufacture a mask reliably and with high yield both from a mask standpoint and from the silicon standpoint. As has been reported earlier, mask manufacturing rules are usually determined from assumed or experimentally acquired/validated mask-manufacturing limits. These rules are then applied during RET/MDP data treatment to guide and/or limit pattern correction strategies. With increasing RET and low-k₁ lithography challenges, the importance of MRCs compounds. Furthermore, it will be necessary to comprehend certain MRC restrictions in the design flow as well as in the RET and MDP space. While mask tool manufacturers will need to be able specify tools specifications relevant to the MRCs for a particular mask shop flow, software tool suppliers, such as for RET, need to do so as well with tools which comprehend, check for, and enforce MRCs consistently. IDMs, foundaries, mask shops, EDA companies and tool suppliers will need a common language for the discussion on MaskDRs and MRCs in order to reach unambiguous convergence. Experience at Texas Instruments shows that accurate description, specification, and interpretation of MaskDRs and applying the associated MRCs is critical to a successful advanced mask technology strategy. This paper proposes the creation of a standard MaskDR lexicon. The goal of such a lexicon is the standardization of MaskDRs and their definitions such that interested parties from various mask-related disciplines can discuss, negotiate, specify, test and enforce MaskDRs unambiguously. We further propose that this standard be machine readable and directly usable without the necessity for intermediate interpretations. This lexicon would allow the designers, IDMs, foundaries, mask suppliers, and equipment suppliers to unambiguously negotiate and agree upon mask manufacturability requirements for their particular application.

Due to photolithography effects and manufacture process variations, the actual features printed on wafer are different from the designed ones. This difference results in the inaccuracy on parasitic extraction, which is critical for timing verification and design for manufacturability. Most of the current layout parasitic extraction (LPE) tools ignore these effects and can cause as high as 20% errors. This paper proposes a new strategy to extract interconnect parasitics with the consideration of photolithography effects and process variations. Based on the feedback from lithography simulation, a shape correction process is setup to adjust the interconnect structure for LPE tools. Compared with the traditional extraction methodology, the parasitics extracted from this adjusted geometry are more accurate. This method can be implanted into the current design flow with minimum change. Meanwhile, this paper studies the impacts of mask critical dimension (CD) variations on interconnect parasitics. The variability analysis is based on PROLITH lithography simulation software and is tested on RAPHAEL interconnect library. The results show a high nonlinear relationship between the mask variation and the interconnect parasitics.

DfM (Design-for-Manufacturability) has become staple requirement beyond 100 nm technology node for efficient generation of mask data, cost reduction, and optimal circuit performance. Layout pattern has to comply to many requirements pertaining to database structure and complexity, suitability for image enhancement by the optical proximity correction, and mask data pattern density and distribution over the image field. These requirements are of particular complexity for Systems-on-Chip (SoC). A number of macro-, meso-, and microscopic effects such as reticle macroloading, planarization dishing, and pattern bridging or breaking would compromise fab yield, device performance, or both. In order to determine the optimal set of DfM rules applicable to the particular designs, Return-on-Investment and Failure Mode and Effect Analysis (FMEA) are proposed.

At 90nm and 65nm, the semiconductor industry is condemned to use 193nm steppers and an overwhelming amount of resolution enhancement techniques (RET). Even when using the best RET solution available, some designs are more amenable to manufacturing than others and their initial yield or startup yield is higher. Design for manufacturing (DFM) has been a hotly discussed topic in both electronic design automation (EDA) and manufacturing communities, and to date much debate remains regarding its precise definition, let alone the solution. However, it is rather intuitive that, whatever the solution is, DFM needs to simultaneously satisfy several objectives in terms of optimizing yield, manufacturing cost and manufacturing friendliness; being transparent to the designer; protecting manufacturing intellectual property (IP); and having a sensible implementation. In this paper, we will describe a suitable technology that satisfies the data information sharing to ensure that both designers and manufacturers fulfill the expected initial and volume yield expectations. We describe how this technology may be applied pre- and post-tapeout to fulfill both designer and manufactures requirements.

At the 65 nm node and beyond, printing the dense and isolated pitches as well as the 2D patterns within tight tolerance across the full range of known process conditions becomes a major challenge, and even more critical in the context of double exposure masks. Post-OPC simulation at nominal conditions is not sufficient to accurately assess and disposition severe errors and monitor residual proximity effects and their implications such as channel length variation. In this paper, we explore a methodology that adopts multiple simulations to model the variability in the lithography process. This approach is predicting the process behavior by the modulation of the related lithography parameters, such as: dose, focus, and overlay. The goal is to identify the unacceptable deviation of the printed image from the designed target due to process variations. The method also provides a better statistical evaluation of the quality and robustness of the implemented Resolution Enhancement Techniques (RET) & Design for Manufacturability (DfM) solution.

Reflections occur at every interface of a mask and are known as flare. Flare effects have a negative impact on the resist exposure at the wafer level. In this paper total antireflection (AR) solutions are presented to eliminate flare effects at mask level. These are next generation binary and phase shifting mask blanks, where AR coatings are effective not only on top of the absorber, but also eliminate internal as well as back side reflections. Substrate reflection can be reduced both internally and externally by an order of magnitude to below 0.5%. Internal (backside) reflection of a binary chrome or a phase shifting layer are reduced from about 40% to below 0.1%. Reflection in the etched area is also addressed and reduced by an order of magnitude. A sophisticated absorber AR coating is presented, where reflection at 193 nm lithography can be reduced to zero while at the same time reflection at 257 nm inspection wavelength is tuned to the maximum sensitivity range of 7% to 20%.

Intensity imbalance between the 0 and π phase features of c:PSM cause gate CD control and edge placement problems. Strategies such as undercut, selective biasing, and combinations of undercut and bias are currently used in production to mitigate these problems. However, there are drawbacks to these strategies such as space CD delta through pitch, gate CD control through defocus, design rule restrictions, and reticle manufacturability. This paper investigates the application of an innovative films-based approach to intensity balancing known as the Transparent Etch Stop Layer (TESL). TESL, in addition to providing a host of reticle quality and manufacturability benefits, also can be tuned to significantly reduce imbalance. Rigorous 3D vector simulations and experimental data compare through pitch and defocus performance of TESL and conventional c:PSM for 65nm design rules.

Bimetallic thin films have been proven to be effective in creating analog direct write grayscale photomasks. DC-sputtered Bi/In or Sn/In oxidizes under laser writing exposure. The optical density decreases from >3OD as deposited to a transparency of <0.22OD at 365 nm with increasing laser power. The bimetallic film has a response curve that is nearly linear for much of the curve, but non-linear at maximum absorption and transmission. In order to create more accurate gray levels, a more gradual OD change versus laser writing power is desired. In this research a new reactive sputtered, oxygenated Bi/In film was created that has an 8-bits grayscale level sensitivity of 1.1 gray levels/mV, compared with the previous Bi/In of 3.2 gray levels/mV and Sn/In of 2.8 gray levels/mV. This modified Bi/In film provides more than twice the laser writing power range for controlling the same OD range, as compared to our original Bi/In or Sn/In films. This wider power range provides easier and more accurate laser power-to-grayscale calibration, because each grayscale can now be spaced more evenly over the increased laser writing power range. In addition, the surface of modified Bi/In is found to be much smoother than the original Bi/In and Sn/In films, thus increasing the overall quality of grayscale photomask. Finally grayscale uniformity of the laser writing process has been investigated and techniques such as laser beam shaping and defocusing have been used successfully to eliminate the variations.

Critical dimension (CD) requirements are continually tightening for mask manufacturing for mean to target and uniformity control as advanced technology nodes are introduced. In addition, the CD repeatability of structures relevant to optical proximity correction is also becoming more critical with each advancing node. Chemically amplified resists commonly in use in the mask industry are sensitive to post coat delay (PCD), storage and handling conditions, and environmental contaminants. In this paper, the CD sensitivity of a commonly used photoresist is characterized as a function of post coat delay. The impact to average CD, uniformity, linearity, thru pitch, clear to dark, and e-beam proximity effect are all examined. An analysis of post develop resist thickness loss is presented to supplement the understanding of CD uniformity behavior. In addition, the impact of several storage scenarios is evaluated including storage in a sealed foil bag, an unsealed dry nitrogen environment, and storage boxes made from two different materials. The impact of storage conditions on CD uniformity is critical and is shown to be strongly influenced by the choice of material for the containers and the storage environment.

Shrinking of pattern size on photomask requires tight control on defects and CD qualities. Recent ultra resolution lithography requires tight criteria for defect. In this paper, we describe the main defect factor "re-adsorption of resist" on. This is dependent on the development process, the relationship between defect and development and/or rinse method. The hp90-65nm process needs to reduce re-adsorption of resist for improvement in defect level. The solution of this issue is the uniformed high flow for development and rinse fluid. We adopt modified development system as the intermediary to make high fluid flow possible. From our results, this system could reduce the number of defects around 70-80%. The defect size will also be reduced through this system. So, we propose that Noble development method is one of the effective process means for hp90-65nm photomask production.

Increasing demand for high end lithography mask especially phase shift masks and narrowing the specification, lead to development of etch processes with minimum critical dimension uniformity (CDU) and very low etch bias. The etch bias becomes one of the limiting parameters for the Cr etch process, due to strong cross links between etch bias and other etch characteristics like linearity and loading effect, thus contributing strongly to the CDU for masks with non uniform pattern distribution. The goal was to develop a Cr etch process with very low etch bias, keeping the other parameters at the same level and providing a wider process window for further optimization of the CDU, loading effect and linearity. In the paper we want to present a feasibility study of one specific approach to the mentioned methods and compare different ways for measurement of the CDU and etch bias. The work presented was done on the Applied Materials Tetra II Mask Etch system.

Dry etching process is widely used in semiconductor field and in photomask manufacturing. Even though dry etching technique can be much better in obtaining straight profile and better CD (Critical Dimension) uniformity than wet etching technique, it has a severe problem in terms of defect issue. Especially, very tough controllability of defects is essential for the photomask dry etching process because defect can be printed on the wafer over. Therefore, we studied defect free photomask etching techniques and found out the possibility of particle evasion. With In-situ etching method, defect generation by MoSiON etching could be reduced compared to when standard etching process is used while the process result is almost same as that of the standard process. In this paper, we will present the experimental result of in-situ. dry etching process technique for Cr and MoSiON, which reduces the defect level significantly.

A robust photomask etching process was studied and developed for 65 nm node photomask production with zero CD process bias. The fabrication process, including pattern generation and transfer do not use data sizing, saving photomask delivery time, improving yield, and reducing fabrication costs. The photomask patterns, without using data sizing cover chrome loads from about 1 percent to 80 percent. For 65 nm critical layer EAPSM, the CD bias of Cr and MoSi etching together is equal to or less than about 20 nm for high and low load photomasks. The etch process and dose adjustment on the 50 keV e-beam writer allow for zero CD process bias, i.e. the data sizing becomes unnecessary in the 65 nm node photomask fabrication. The SMIF pot utilization in both pattern generation and transfer processes significantly improved the defectivity control. Cr and MoSi etch endpoints of 1% load photomasks were clearly detected. Point-to-point CD etch contributions for dark and clear features are 5 nm (3 sigma) or less and final CD value ranges are 8 nm or less. CD etch linearity and other etch properties on SRAF and serif are also discussed. An equation was proposed for calculating phase angle non-uniformity distribution, and phase angle range can be controlled in the range of 1.4±0.3 degree. "Self-mask", i.e. using AR sub-layer as hard mask for beneath chromium sub-layer etch was also discussed.

The photomask industry is constantly reaching towards next-generation technology that can advance today's semi-conductor applications. One of the most successful and widely used techniques for advancing the current lithography capability and meeting many of the next-generation requirements is through the use of phase-shifting photomasks (PSM). Resolution enhancements techniques implemented through the use of PSMs can be a powerful tool in meeting both today's and tomorrow's demanding lithographic requirements. For this work, effects of changing etch process parameters on the quartz dry-etching process performance is investigated. Considerations are given to phase depth uniformity, sidewall profile and reactive ion etch lag in the analysis of the quartz etch performance.

Despite the complexity of AAPSM patterning using the complementary PSM approach with respect to OPC correction, mask making, fab logistics etc, the technique still remains a valuable solution for special products where a low CD dispersion printing process is required. For current and next generation process technologies (90-65nm ground rules), the most common alternating mask solution of single trench etch with or without undercut becomes more difficult to manufacture. Especially challenging is the aspect ratio control of quartz etched trenches as a function of density in order to assure the correct phase angle and sidewall for dense and isolated structures over all phase shifted geometries. In order to solve this problem, a modified mask architecture is proposed, called the Transparent Etch Stop Layer (TESL) phase shift mask. In TESL, a transparent (etch stop) layer is deposited on the quartz substrate, followed by the deposition of a quartz layer having a thickness corresponding to the required phase angle for the used wavelength. On top a Chromium layer will be deposited. The patterning of this mask will be quite similar to the single trench variant. The difference is, that now an overetch can be applied for the phase definition resulting from the high etch selectivity of quartz to the etch stop material. The result of this approach should be that we can better control the phase depth and sidewall angle for dense and isolated structures. In this paper we will discuss the results of the printing tests performed using TESL masks especially with respect to litho process window, and we will compare these with the single trench undercut approach. Simulation results are presented with respect to shifter sidewall profile and TESL thickness in order to optimize image imbalance. Throughout the study we will correlate simulations and measurements to the after-MBOPC CD values for the shifter structures. These results will allow us to determine if the TESL AAPSM approach can be a more effective alternative to the single trench undercut approach.

Photomasks to support 45nm node circuit development will be needed by mid year 2007 to meet the most aggressive device development programs. Volume manufacturing of 45nm technology photomask, however, would not occur until 2-3 years later. Either case would require an advanced photomask lithography capability that can meet the 45nm node specifications. From a mask maker's perspective, a lithography tool platform that is flexible, that supports high resolution and can be ramped for throughput would be the best solution. In an effort to understand if a potential tool platform(s) will exist, Photronics performed characterization and assessment studies of all commercial mask pattern generator platforms. All mask pattern generator tools, including both e-beam and laser platforms, were evaluated for performance against 45nm node target specifications as defined by the International Technology Roadmap for Semiconductors.

This paper is a comparison of different gray scaling techniques used in optical mask making. It shows that high address resolution and high throughput can be combined with the lithographic performance necessary for the most advanced applications. In the semiconductor industry, Moore's law continues to describe the ever-increasing demand for better performance in terms of clock-frequency and circuit density. One effect is shrinking design grids to cope with the tighter requirements on resolution, CD control, and aggressive OPC. For mask making this means that the address resolution of the mask writing equipment must be improved for every tool generation. The address resolution in the mask writer can be increased in two ways; either by decreasing the physical grid, or by introducing a virtual grid by using gray scaling. In the former case, the throughput, a performance parameter of utmost importance for reasonable mask costs and cycle times, will suffer a high penalty. In the latter case, however, a fine address grid is created, while keeping a large physical grid for high throughput. In earlier publications, a single pass raster scan gray scaling technique has been shown to reduce image quality in terms of image log-slope. This paper shows that the effects are kept to a minimum in the SLM-based DUV Sigma7300 mask writer, which uses partial coherent imaging and multiple writing passes. Analysis shows that the reduction in image log-slope due to gray scaling is less than 8%. In addition, the systematic averaging of four displaced writing passes makes the loss isotropic and independent of grid position. A detailed error analysis shows that a small address grid is more important for composite CD uniformity than the loss in image log-slope.

Currently, the ALTA 4300 generation Deep Ultra-Violet (DUV) Laser tool is capable of printing critical and semi-critical photomasks for the 130nm and 90nm IC technology nodes. With improved optical elements, an improved objective lens, and a higher bandwidth datapath the capability of the tool has been dramatically enhanced. Both the tools diffractive optic element (DOE) and acousto-optic modulator (AOM) have been refined. Additionally, the tools 33x, 0.8NA objective lens has been replaced with a 42x, 0.9NA objective lens. Finally, the tools datapath enhancement has allowed critical level write times to remain less than four hours. Quantitative results of these enhancements will be detailed through reporting of critical feature resolution limits, CD uniformity control, and pattern placement accuracy on mask. Performance will be shown from masks printed pre- and post- hardware upgrade. Experimental results will show actual improvements. In this paper details of the aerial image created when printing wafers with DUV Laser generated photomasks pre- and post-upgrade will be shown. Both 248nm and 193nm source printing with multiple illumination conditions will be discussed. Details of a print test comparison performed on photomasks from each tool configuration will be documented. The print test comparison will include process window characterization from each mask type. A study of the inspectability of the DUV Laser generated photomasks will also be highlighted.

SLM-based DUV laser writers are gaining acceptance for 2^nd level PSM and binary mask patterning. These writers can use an e-beam compatible resist enabling tool and process sharing. For binary mask patterning, critical metrics include: critical dimension uniformity (CDU), CD targeting, mask registration, defect performance and inspectability. For PSM applications, pattern fidelity matching to 1^st level and PSM overlay are also important. A Sigma7300 is being integrated into 65nm and 45nm production. Binary and PSM mask performance data will be presented. Tool self metrics to characterize SLM health will also be presented. Data conversion, data preparation and production write times will be discussed.

The ALTA 4700 incorporates new optical subsystems to improve pattern quality performance and has added the capability to do variable multipass printing. The optical system changes are the addition of a 0.9-NA reduction lens and a new AOD subsystem to reduce beam placement and intensity errors. Variable multipass printing allows two-, four- or eight-pass printing, thereby enabling the user to optimize the pattern quality/throughput tradeoff. Local CDU 3σ performance for one pattern is reduced from 8.2 to 5.1 to 3.4 nm as the number of passes is increased from two to four to eight. Reduction of CDU performance is more pattern dependent going from four to eight passes than going from two to four passes. Pattern write times scale roughly linearly with the number of passes. Local pattern loading effects can limit global CDU performance. These effects can be reduced by optimizing resist selection and develop processes.

As 193 nm lithography appears to be a long term solution for wafer patterning, we expect new resolution enhancement coming from advanced mask technologies. We have studied an assembly technique that could increase mask capability towards advanced wafer patterning. This paper presents a proof of concept for the use of bonded mask, obtained with two plates assembled together. The initial application targeted here is an alternative solution to pellicle. A special process has been worked out to obtain bonded test samples. Based on the knowledge of silicon wafer bonding techniques, we have developed a process that allows bonding of fused silica square plates. Constant progress allowed us to use specific materials used in mask manufacturing, such as chromium and fused silica, and also specific square shapes and rather large thickness. The final demonstrator is a Chromium on Glass mask (COG), on which a hard pellicle has been bonded without any additional material. The pellicle was 0.5 mm thick and 100 mm in diameter. This test sample has been qualified in a 248 nm AIMS tool. We made comparative measurements on different occurrence of the same chip, covered or not covered by the pellicle. We have shown evidence of induced spherical aberration for conventional illumination and this has been confirmed by simulation. Image fidelity was proven for positive and negative features. Through focus image capture showed that process windows were not impacted by the hard pellicle.

This paper presents the first results on mask critical-dimension (CD) specifications for the hyper-numerical aperture (hyper-NA) lithography. The mask CD specifications have been derived from experimental results applying the immersion lithography with NA being 0.85. The experiment has been performed for a hole pattern corresponding to the 65-nm node with NA = 0.75 or 0.85. From this experiment, it was found that the higher-NA condition (NA = 0.85) makes the mask CD tolerance being more than doubled as compared to that under the lower-NA condition of NA = 0.75 while retaining the depth-of-focus (DOF) margin. This relaxation in the CD tolerance is attributable to the enlargement of DOF in the immersion lithography where the DOF becomes more than n times larger than that with the dry lithography under the same resolution limit (n: refractive index of immersion fluid). Analyses of the mask CD tolerance have been performed by applying a newly-developed method, that enables a quantitative analysis of mask CD error and DOF margin. In addition, the mask CD error margin for the 45-nm node have also been estimated by performing a lithography simulation under conditions with NA = 1.07 and 1.20. From this simulation, it was predicted that for the case when NA = 1.07, the mask CD error margin requires specifications on mask that are almost unachievable if one concerns the status of current mask manufacture processes together with the forecast on the processes given in the ITRS 2004 roadmap. On the other hand, the simulation predicted that the higher-NA condition (NA = 1.20) with the immersion imaging realizes a relaxation in the mask CD tolerance, leading to realistic specifications on mask. Therefore, this strategy realizes a breakthrough to avoid the "mask crises".

Thin mask approximations and Kirchhoff boundary conditions for imaging calculations are justified when patterns on masks are large compared to the imaging wavelength and the thickness of absorber films were relatively small compared with the wavelength. For the future technology nodes, these assumptions will not be sufficiently accurate for simulation of attenuated phase shift masks. At very high numerical apertures and extreme off-axis illumination angles, changes in the optical path length and shadowing by the mask topography can lead to phase and amplitude deviations between the thin mask approximation and the more rigorous, full Maxwell equations approach. We have found a systematic, non-constant transmission and phase variation through pitch for low k1 imaging that is not found with the thin-mask approach. In this paper, the major impacts of attenuated phase shift mask topography in the presence of extreme off-axis illumination with numerical apertures greater than one is investigated and the contribution of mask topography to CD errors on the wafer is explored. Consideration of this new mask component to CD error budgets is needed when debating the advantages and disadvantages in a reticle magnification change.

The introduction of polarized light in high NA lithography requires additional characterization metrics for illumination systems. It has been shown that the percentage of the total light intensity that is polarized in the desired direction is a metric that can be closely related to wafer CD. On ASML systems, this quantity is called IPS (Intensity in Preferred State). Illuminators are characterized in terms of the minimum IPS found somewhere across the illuminated area and the IPS Range. In case the mask has a finite birefringence, there is an additional impact on the effective IPS. After passing through the mask blank, the IPS of the light will have changed and hence, there will be a response for wafer CD. Mask birefringence in conjunction with IPS introduces an additional contribution for the CD budget. This work will focus on the impact of mask birefringence on wafer CD for different scenarios of polarized illumination. We will show that the angle of the fast axis of birefringence can have a much greater impact on CD than the maximum birefringence magnitude itself. Based on these results we will derive a requirement for mask birefringence which has its foundation on CD. We will present measurements of the birefringence distributions of mask blanks, patterned masks, and masks with pellicles to investigate the contribution of the mask process flow starting from substrate, material deposition, processing, and final pellicle application. In addition to the material properties of the pellicle, the mounting of the pellicle to the substrate may induce additional stress birefringence.

Mask data file sizes are increasing as we move from technology generation to generation. The historical 30% linear shrink every 2-3 years that has been called Moore's Law, has driven a doubling of the transistor budget and hence feature count. The transition from steppers to step-and-scan tools has increased the area of the mask that needs to be patterned. At the 130nm node and below, Optical Proximity Correction (OPC) has become prevalent, and the edge fragmentation required to implement OPC leads to an increase in the number of polygons required to define the layout. Furthermore, Resolution Enhancement Techniques (RETs) such as Sub-Resolution Assist Features (SRAFs) or tri-tone Phase Shift Masks (PSM) require additional features to be defined on the mask which do not resolve on the wafer, further increasing masks volumes. In this paper we review historical data on mask file sizes for microprocessor designs. We consider the consequences of this increase in file size on Mask Data Prep (MDP) activities, both within the Integrated Device Manufacturer (IDM) and Mask Shop, namely: computer resources, storage and networks (for file transfer). The impact of larger file sizes on mask writing times is also reviewed. Finally we consider, based on the trends that have been observed over the last 5 technology nodes, what will be required to maintain reasonable MDP and mask manufacturing cycle times.

In the IC process, the designed circuit pattern is drawn onto film or glass plate as a photo mask. This original mask is used to transform its transparent pattern onto semiconductor wafers by optical projection. To make photo mask we should convert the design data into a format that the e-beam write tool can understand. This MDP (Mask Data Preparation) process is getting more and more complicated to support many kinds of e-beam data format which is required not only for each electron beam writers but die to database inspection tools. It gives us a burden to treat various MDP flow and this may impact on turn around time (TAT). Therefore, it becomes more necessary to make MDP flow simpler by unifying the various mask data formats. Moreover it is required to suppress huge data volume due to design rule shrink and aggressive OPC. To address these issues, the Open Artwork System Interchange Standard (OASIS^TM) has been approved by the EDA industry and is officially announced by SEMI Data Path Task Force. OASIS data format allows the reduction in file size compared to GDSII while the processing time such as MRC and MDP is not influenced. Also OASIS is effective in reducing complexity of mask data preparation flow. In this paper, the implementation of OASIS format within mask data preparation flow will be discussed and experimental results of OASIS-based data flow will be shown with comparing to traditional GDSII/MEBES-based data flow.

Filling for the prevention of CMP dishing and resolution enhancement technologies (OPC, PSM) can cause the size of IC designs represented in the popular GDSII Stream format to balloon by a factor of ten or more, resulting file sizes of tens of gigabytes and longer throughput times for the tools that must subsequently process the files. We describe the effects of optimizing GDSII Stream files on the tape-out flow. GDSII Stream file sizes can be reduced by as much as 95% (20X reduction) and subsequent tool throughput improved by factors of up to five (5X runtime improvement).

As the critical dimension (CD) becomes smaller, various resolution enhancement techniques (RET) are widely adopted. In developing sub-100nm devices, the complexity of optical proximity correction (OPC) is severely increased and applied OPC layers are expanded to non-critical layers. The transformation of designed pattern data by OPC operation causes complexity, which cause runtime overheads to following steps such as mask data preparation (MDP), and collapse of existing design hierarchy. Therefore, many mask shops exploit the distributed computing method in order to reduce the runtime of mask data preparation rather than exploit the design hierarchy. Distributed computing uses a cluster of computers that are connected to local network system. However, there are two things to limit the benefit of the distributing computing method in MDP. First, every sequential MDP job, which uses maximum number of available CPUs, is not efficient compared to parallel MDP job execution due to the input data characteristics. Second, the runtime enhancement over input cost is not sufficient enough since the scalability of fracturing tools is limited. In this paper, we will discuss optimum load balancing environment that is useful in increasing the uptime of distributed computing system by assigning appropriate number of CPUs for each input design data. We will also describe the distributed processing (DP) parameter optimization to obtain maximum throughput in MDP job processing.

This is a report of the panel discussion in PMJ 2005 on April 16, 2005. We discussed in the session on the technologies of photomask for hyper-NA lithography, with six invited panellists of two from LSI manufacturers, a lithography researcher, one from a lithography tool supplier, one from an EDA vendor and one from a photomask supplier. First, we had short presentations by the panellists on the issues brought about by hyper-NA lithography from their own technological points of view, and we knew their extensive efforts to overcome the difficulties in hyper-NA lithography. By the presentations, we had been impressed that ArF immersion technique was almost one and only promising candidate of the lithography methods which we could employ in the technology nodes of 65nm and beyond, and, that the technologies for hyper-NA lithography were then already within our hands. We discussed the difficulties inherent to hyper-NA lithography and recognized the needs of further engineering efforts to obtain maximal performance in the lithography. There were some who expressed the necessity of the change of photomask magnification because of the compatibly small features on a photomask to using wavelength in the lithography. The attendants could confirm the positions of their opinions by the insitu statistic results of the questionnaire we had had in the conference.

An extremely fast time-harmonic finite element solver developed for the transmission analysis of photonic crystals was applied to mask simulation problems. The applicability was proven by examining a set of typical problems and by a benchmarking against two established methods (FDTD and a differential method) and an analytical example. The new finite element approach was up to 100 times faster than the competing approaches for moderate target accuracies, and it was the only method which allowed to reach high target accuracies.

Mask manufacturers and mask users continue to pursue improvements in mask inspection and qualification processes driving standards to guarantee the highest performance of advanced photomasks while maintaining a high degree of predictability of turn-around-time. Simulation-based defect analysis and dispositioning has become an area of much interest for both mask manufacturers and mask users. Repairing only the defects that impact wafer level performance (lithographically significant) improves both mask cycle time and eliminates unnecessary and costly repairs. Mask maker and mask users can utilize defect simulation as a common standard by which to benchmark the quality of results. We report in this paper the results of a joint evaluation of the i-Virtual Stepper system (i-VSS) the automated simulation based defect dispositioning software solution in an advanced photomask qualification flow. Results discussed include the optimization and automation of the mask inspection flow using i-VSS, simulation accuracy comparisons of i-VSS versus AIMS versus wafer printability for binary and phase shifting masks at 130nm, 90nm, and 65nm technology nodes, and a comparison of the iVirtual Stepper system's automated defect severity scoring (ADSS) versus manual defect dispositioning.

Ultra high numerical aperture (NA) enables extension of ArF lithography for the 45 technology node and beyond. The resulting changes in design rules drives feature sizes on the mask into the sub-wavelength regime. As 2-beam imaging techniques (off-axis illumination and alternating phase shift mask) are required for strong resolution enhancement in low-k1 lithography, traditional scalar and paraxial approximations used for optical image modeling are no longer valid in the ultra high NA regime. Vector and thick-mask based models are required to account for topographic effects and large angles of incident light at the reticle plane in ultra-high NA systems. Although vector-based imaging theory is well understood, experimental validation is required to ensure the appropriate topographical and optical parameters are being used. To address these issues, finite-difference time-domain rigorous electromagnetic simulation are compared to experimental measurements of the polarization dependent diffraction efficiencies on advanced optical reticles. Based on these results, the impact of mask induced polarization to vectorial imaging latitude is assessed. The impact of polarization purity, mask absorber profile, and Fresnel effects through the pellicle on process window and OPC are also discussed.

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist, they have often a large number of parameters to fit and suffer from long computing times to execute the simulations. Simplified resist models are thus needed to enhance run-time computing during simulation. The objective of this study is to test the predictability of such resist models across the process window. Two different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific simulations obtained with the two different techniques are compared against experimental results.

The reticle manufacturing process induces various defects on the mask that need to be repaired. Missing absorber or clear defects are often repaired by depositing a carbon-based material (depo) using a Focused Ion Beam (FIB) tool. Few cases of such depo repairs on defects in between nested contacts on attenuated phase shift masks were found to fail upon use in high volume wafer manufacturing factories. With the goal of first reproducing the problem in the mask shop, a controlled set of depo repairs were performed on a test reticle and sequentially exposed on a DUV flood exposure system, emulating stepper exposure. The repair AIMS^TM printability and AFM height profiles were measured before and after each exposure step. With incremental exposures, AIMS^TM results showed the repaired contacts gradually printing larger in size and AFM results showed the tail of the depo repair (also referred to as depo overspray or halo) correspondingly receding with exposure. This suggests that the tail of the depo presumably contributes to the correct print CD of the repaired contact, and its gradual recession with exposure was likely causing the contacts to print larger, ultimately even bridging with the neighboring nested contact in some cases. This mechanism was confirmed by checking similar repairs on several production masks already being used in the wafer factories, at different stages of exposure. Subsequently, a novel post-repair process was developed which achieves rapid overspray removal thereby avoiding any further change in these repairs and associated wafer yield impact upon prolonged use on scanners.

As current feature size on mask is under the wave length of inspection source, it is difficult to distinguish a defect where it is on or from, even though high NA optic lens is used. The disadvantage of this hi-res defect detection method require review step which spend much of inspection time. So this lack of resolution of optical inspection tool requires new review tools such as SEM (Second electron Beam Microscope) or FIB(Focused Ion Beam). As the image of ion beam generally shows speckle noise, we adapted anisotropic nonlinear diffusion technology to remove noise without loss of pattern, by different diffusion along pattern edge. And a fine defect image by image processing to repair was extracted to replace the pattern copy function of FIB.

In prior work, the capability of mask-topography (AFM) based photolithographic simulation (SOLID-C^TM) to minimize the number of aerial image microscope simulation (AIMS^TM) evaluation related mask load/unload cycles in a repair tool was demonstrated for programmed binary edge defects at 248 nm wavelengths and various stages of defect repair. The next stage is to bring the concept of photolithographic mask simulation concurrent with defect repair closer to a production-level system. This was done by comparing SOLID-C^TM simulations generated directly from uploaded AFM topography data with 193 nm AIMS^TM results for a set of patterns and defect repairs. The results have been successfully compared in both best and through-focus evaluations. With this increased knowledge and experience, it becomes possible to not only increase the efficiency and yield of the repair of any mask defect, but to also further optimize each individual repair with feedback as to the potential impact on the lithography process.

Several haze studies were conducted in a test environment where UV lamps and test chambers were used to simulate a wafer fab environment. This study was designed to investigate reticles experiencing different cleaning processes in a real wafer production environment. A split test was carried out to benchmark two different fabs: an 8" R & D fab and an 8" memory production fab. Reticles cleaned with UV treatment and hot DI water were exposed on ArF scanners for up to 80 hours over a period of two months. Starlight inspection before and after laser exposure confirmed no significant defect count increase after exposure. Ion chromatography (IC) results from masks cleaned on a new Steag MaskTrack cleaner suggest that hydrogenated water (H₂-H₂O) and ozonated water (O₃-H₂O) processes can further reduce the sulfate and ammonium ion residual count by 40%. UV + hot water cleaning also shows advantages in phase and transmission preservation where less than a 0.2 degree phase angle loss per clean can be achieved.

This is an experimental result for the inhibition of effects of the growing defect. Up to now, it has been considered and defined that the growing defect is an unexpected and unusual reaction by bonding impure ions existed on the mask each other. This study is not only to suppress the unexpected reaction when making the final mask but also to stabilize the surface of mask by controlling by-product occurred when stripping upper Cr layer and damaged layer from sputtering process. According to the analysis of the surface roughness stemming from each process (from wet etching to cleaning Process) of MoSi layer, the surface still comes to be rough when a mask is done through all process. So, heat treatment was performed and surface roughness was measured to figure out how much the surface condition would be improved and how many remaining SO4, NH4 Ions on the surface after cleaning process reduced. This study shows the major factor causing plasma damage is a dry etcher, a way to control the damaged layer of MoSi at PR strip process, the level of stabilization of mask surface through cleaning process and a clue to be able to prove the stabilization by adding specific process. Analysis tools for this study are as follows. AFM (for checking the roughness of surface), TEM (for checking cross-section) and IC (Ion chromatography)analysis equipment.

Sub-pellicle defects and haze increase due to photon reaction with cleaning chemistry residues are especially problematic on photomasks for 193 nm and shorter exposure wavelengths. In addition to mask cleaning, these chemistries are also used for photoresist stripping from photomasks. In this paper sulfuric acid free processes are shown to be effective for mask cleaning and photoresist removal. Bulk removal of photoresist was accomplished with both oxygen based dry plasma stripping and with wet oxidizing chemistry. Surface preparation prior to the main cleaning step was necessary to render Cr surface hydrophilic and enable targeted cleaning performance. This was accomplished with an O₃/DI pre-treatment step. Full mask megasonics improved particle removal efficiency of moderately to heavily contaminated masks.

This paper describes a new surface cleaning approach for photomask cleaning. This non-conventional cleaning method uses momentum transfer between aerosolized, frozen, CO₂ particles and the contaminants for effective removal from surface. The purity of CO₂ used is an important component in the determination of cleaning efficiency. The authors will present two methods developed to analyze hydrocarbon contamination in CO₂. These analytical methods were used to compare different grades of CO₂ including Ultra High Pure (UHP) grade developed for sub-micron particle removal from photomasks. Using the UHP grade CO₂, it was shown that greater than 99% particle removal efficiency is possible from silicon wafer surfaces, with higher removal efficiency of sub-micron particles compared to larger size range. This particular characteristic of particle removal by cryogenic aerosol method is theoretically derived in an earlier paper. In this paper results of CO₂ cryogenic aerosol cleaning with respect to electrostatic discharges on two different binary masks are presented. The paper also shows the removal of 99.9% of the progressive defects such as haze of 0.5 to 1.0 μm size. Cleaning characterization of attenuating phase shift masks with MoSiON films indicate 0.04% change in transmission and 0.37% change in phase angle after 16 cleaning cycles, suggesting that cryogenic cleaning has minimal effect on transmission and phase of att-PSM.

In this paper, we report on a Scatterometry based metrology system that provides line width and thickness measurements on binary, APSM, EPSM masks both on FCCD (final check CD) and DCCD (develop check CD), fabricated on 193nm process. Measurements were made with scatterometer in DUV to visual wavelength range. Calculation of profile information was performed by a library-based analysis software. We characterized the CD uniformity, linearity, trench depth uniformity. Results show that linearity measured from fixed-pitch, varying line/space ratio targets show good correlation to top-down CD-SEM, meanwhile linearity from wide range of different pitch generally does not correlate well and therefore post-measurement calibration is needed. Depth measurements from APSM show that scatterometer makes good correlations to AFM. The effect of optical properties of the film layers on metrology performance is discussed. The data show that Scatterometry provides a nondestructive of monitoring basic etch profile combined with relatively little time loss from CD measurement step.

Accuracy and fabrication cost of optical masks continue to be major concerns for the semiconductor industry. While immersion and other process technologies promise to extend optical lithography down to the 45nm node, the resulting technical and commercial requirements for the mask fabrication process become increasingly difficult to achieve. Potential solutions that are readily available to wafer fabricators are either too expensive to deploy or have not been commercialized for mask manufactures- up until now. Mobile metrology has the inherent ability to provide the required measurement accuracy, on any tool, at a low cost of ownership. This paper will discuss the application of a self-contained, wireless SensorPlate for providing process optimization and control within a leading mask blank manufacturing facility. Three critical process steps are characterized: Quartz Cleaning, Chromium Physical Vapor Deposition, and Photoresist Post-Applied Baking. Process optimization was completed to achieve improved performance of the mask blank product.

With photolithography being pushed to its limits, semiconductor device performance is becoming increasingly more sensitive to lithographic variations. More advanced lithography tools, metrology and photomasks are helping address issues like minimum feature size, tight CD control, and limited process windows. Mask registration is becoming even more important in the low k1 regime, where overlay can have a huge impact on the overall device performance and drive the error budget into unsatisfactory compromises. FLASH memory technology requires a tighter overlay control compared to logic devices. Charge retention and programming performance are particularly sensitive to overlay. In this paper, we analyze the impact of photomask registration on NOR FLASH memory fabrication using Exploratory Data Analysis approach.

Image contrast enhancement, resolution improvement and accurate height information are obtained by near-field induced polarization imaging using a solid immersion lens (SIL) microscopy. A semiconductor PC processor is investigated by this imaging technology. With 520nm linear polarization illumination, around 100nm feature size is resolvable, and topographical information is also achieved from this induced polarization image. We demonstrate this near-field induced polarization imaging is a fast acquisition, large field and high resolution metrology solution.

We evaluated the accuracy of the simulation based on mask edge extraction for mask pattern quality assurance. Edge extraction data were obtained from SEM images by use of TOPCON UR-6080 in which high resolution (pixel size of 2nm) and fine pixel SEM image (8000 x 8000 pixels) acquisition is possible. The repeatability of the edge extraction and its impact on wafer image simulation were studied for a normal 1D CD prediction and an edge placement error prediction. The reliability of the simulation was studied by comparing with actual experimental exposure results with an ArF scanner. In the normal 1D CD prediction, we successfully obtained good repeatability and reliability. In 65nm node, we can predict a wafer CD with the accuracy of less than 1 nm using the simulation based on mask edge extraction. In the edge placement error prediction mode, the simulation accuracy is ~5 nm including edge extraction repeatability and the uncertainty of lithography simulation model. The simulation with edge extraction more accurately predicts the resist pattern at line-end in which the actual mask pattern may be varied from the mask target (CAD) than a conventional simulation in which CAD is used as a mask pattern. This result supports the view that the wafer simulation with edge extraction is useful for mask pattern quality assurance because it can consider actual mask pattern shape.

Sub-resolution assist features are an important tool for improving process robustness for one-dimensional pattern features at advanced manufacturing process nodes. However, sub-resolution assist feature development efforts have not generally considered optimization for process robustness with two-dimensional pattern features. This generally arises both from conservatively placing SRAFs to avoid the possibility of imaging, and from a desire to simplify SRAF placement rules. By studying two-dimensional features using a manufacturing sensitivity model, one can gain insight into the capabilities of SRAFs regarding two-dimensional pattern features. These insights suggest new methodologies for shaping assist features to enhance two-dimensional feature robustness. In addition, a manufacturing sensitivity model form can be employed to optimize the placement of multiple competing SRAFs in localized two-dimensional regions. Initial studies demonstrate significant pullback reduction for two-dimensional features once SRAF placement has been optimized using the manufacturing sensitivity model form.

Different types of phase shifting masks in combination with the proper illumination condition are widely used to allow 193nm lithography to print ever-decreasing pitches with sufficient process window. A viable option for the 65nm and 45nm node is chromeless phase lithography (CPL), which combines a chromeless phase shift mask and 193nm off-axis illumination. Previously, we demonstrated that imaging-wise the π-shift is not entirely reached in narrow mask features, although etched to the nominal etch depth. This is caused by the mask 3D effect, and manifests itself in through focus Bossung tilt/shift issues. In particular, 3D mask simulations suggested that an effective π phase shift could be recovered for the narrow chromeless mask features by applying a larger than nominal etch depth. In this work, the applicability of this solution is considered in more detail. Experimental through-pitch solutions for regular line/space patterns using CPL, obtained on three latest generations of ASML ArF scanners: 0.75NA (PAS5500 /1100), 0.85NA (XT:1250Di), and 0.93NA (XT:1400i) are demonstrated. Importantly, it is illustrated that mask etch depth adjustment is a widely applicable practical solution to the CPL Bossung tilt/shift issue. The effect of source shape, increasing NA, as well as the effect of immersion versus 'dry' lithography is evaluated. Additionally, the ultimate resolution limits at 0.93NA (XT:1400) are explored. Data obtained on a Zeiss AIMS fab193i shows to be in line with both the exposure data and the 3D simulated data, confirming the clear reduction of focus tilt/shift when using the larger than nominal etch depth.

Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intel's 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2^nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2^nd level to the 1^st level binary pattern, i.e. the 2^nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2^nd level DC (develop check) overlay measurements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown that this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC - FC (final check) overlay correlation and the overlay linearity (periphery vs. indie), are discussed.

The technical challenges in using F2 lithography for the 45nm node, along with the insurmountable difficulties in EUV lithography, has driven the semiconductor chipmaker into the low k₁ lithography era under the pressure of ever decreasing feature sizes. Extending lithography towards lower k₁ puts heavy demand on the resolution enhancement technique (RET), exposure tool, and the need for litho friendly design. Hyper numerical aperture (NA) exposure tools, immersion, and double exposure techniques (DET's) are the promising methods to extend lithography manufacturing to the 45nm node at k₁ factors below 0.3. Scattering bars (SB's) have become an integral part of the lithography process as chipmakers move to production at ever lower k₁ factors. To achieve better critical dimension (CD) control, polarization is applied to enhance the image contrast in the preferential imaging orientation, which increases the risk of SB printability. The optimum SB width is approximately (0.20 ~ 0.25)*(λ/NA). When the SB width becomes less than the exposure wavelength on the 4X mask, Kirchhoff's scalar theory under predicts the SB intensity. The optical weighting factor of the SB increases (Figure 1b) and the SB's become more susceptible to printing. Meanwhile, under hyper NA conditions, the effectiveness of "subresolution" SB's is significantly diminished. A full-sized scattering bars (FSB) scheme becomes necessary. Double exposure methods, such as using ternary 6% attenuated PSM (attPSM) for DDL, are good imaging solutions that can reach and likely go beyond the 45nm node. Today DDL, using binary chrome masks, is capable of printing 65 nm device patterns. In this work, we investigate the use of DET with 6% attPSM masks to target 45nm node device. The SB scalability and printability issues can be taken cared of by using "mutual trimming", i.e., with the combined energy from the two exposures. In this study, we share our findings of using DET to pattern a 45nm node device design with polarization and immersion. We also explore other double patterning methods which in addition to having two exposures, incorporates double coat/developing/etch processing to break the 0.25 k₁ barrier.

The use of an Alternating Phase-Shift Mask (AltPSM) is a strong resolution enhancement technique combining high contrast and a low Mask Error Enhancement Factor with a large focus depth. However, image (or intensity) imbalance, which is intrinsically related to AltPSM imaging, is known to produce focus-dependent feature shifts. The evolution towards hyper NA immersion lithography systems and the associated shrinkage of feature sizes and pitches also puts stronger demands on the placement of the printed features, in order to meet the overlay requirements. Therefore, a good image imbalance reduction strategy is important for a successful implementation of AltPSM in manufacturing. A first step towards this implementation is to find a through-pitch imaging solution guaranteeing both the line width and line position to be within CD and overlay specifications in a sufficiently large dose-focus window. In this paper, we present a strategy to evaluate AltPSM imaging results by monitoring the edge displacement of the printed feature caused by image imbalance. The proposed method insures correct line printing within the calculated process window, taking image imbalance into account. We experimentally assess the imaging performance of a current state-of-the-art dry etched AltPSM with a nominal trench bias on a 0.85 NA immersion scanner. The results demonstrate that a through-pitch solution for printing 65 nm lines on wafer from P140 nm to isolated lines exists that meets both the CD and overlay requirements. Moreover, we have developed a methodology that effectively solves the image imbalance using a pitch-dependent trench bias in combination with an optimized etch depth, which should be chosen in accordance with the dose used for printing the 65 nm line.

Alternating PSM (Alt-PSM) has been recognized as a logical Resolution Enhancement Technique (RET) candidate for the 65nm technology node. One of the key properties this technique has to offer is high Depth of Focus (DOF) and lower Mask Error Enhancement Factor (MEEF). The so-called image imbalance is an Alt-PSM specific property which, if not dealt with correctly, constrains the added DOF. Because of mask topography, intensity differences caused by light scattering become evident between π (180°) and zero degree phase shifters. This causes a line shift that is inversely proportional to the pitch. The traditional solution of applying a fixed trench bias increases the width if the π phase shifter to level out intensities and thus minimize image imbalance. This technique may no longer be sufficient at the 65nm technology node. With the requirement to print even smaller pitches together with a tighter Critical Dimension (CD) budget, intensity imbalance is a larger concern. It may be necessary to apply a pitch dependent or variable trench bias. In this paper, we present a practical OPC modeling approach that accounts for image imbalance. The 2D modeling approach uses boundary layers to represent the 3D effect of light scattering. We demonstrate that with the boundary layer model, it is possible to predict image imbalance caused by mask 3D effects. The model can then be used either to determine the nominal trench bias or can be integrated into the OPC engine to apply a variable trench bias. Results are compared to rigorous Electro Magnetic Field (EMF) simulations and experimental exposures using an ArF scanner, targeting pitches of 130nm and above.

This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.

We present Optical Proximity Correction (OPC) model calibration flow which extracts printing shapes from the Scanning Electron Microscope (SEM) pictures, combines this information with CD measurements, and uses it to build OPC models. Such massive calibration comprehensively covers one- and two-dimensional printing effects, and ensures accurate corrections under widely varying proximity conditions.

Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works. The goal of design-aware OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.

Optical proximity corrections (OPC) applied to design layouts are targeted for the nominal process condition F_oE_o that maintains manufacturing throughput and yield. For designs at 130 nm and above, this is usually sufficient to provide the needed resolution enhancement technology (RET) corrections for high-yield manufacturing. However, for sub-100 nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencor's DesignScan tool simulates the performance of a design across the process window and detects any defects which are then flagged for repair. In the conventional OPC flow, correction of defects entails changing the OPC recipe and redecorating the entire layout. Aprio's reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations. This allows prior OPC results to be re-used. The halo or boundary areas associated with the stitching of the modified OPC are simulated and verified and the results are converged back into the layout. This allows the designer to start with a nominal OPC design and by applying reconfigurable OPC technology, eliminate printability errors in the process window, expand the process window, resulting in more robust design performance across the process window. This mask design inspection and optimization method improves yield and shortens cycle time to first wafers, thus providing closure for the design to manufacturing loop.

To shorten the turn around time and reduce the amount of effort for SRAF insertion and optimization on any arbitrary layout, a new model-based SRAF insertion and optimization flow is developed. It is based on the pixel-based mask optimization technique [1] to find the optimal mask shapes that result in the best image contrast. The contrast-optimized mask is decomposed into main features and assist features. The decomposed assist features are then run through a simplification process for shot count reduction to improve mask writing throughput. Model-based Optical Proximity Correction (OPC) is applied finally to achieve required pattern fidelity for the current technology. In this flow, main features and assist features are allowed to be optimized simultaneously such that the effect of SRAF optimization and Optical Proximity Correction (OPC) are achieved. Since the objective of the mask optimization is the image fidelity, and there is no light coming through assist features (in dark field case), the assist features were ensured not to print even with high dose. The results on 65nm/contact layer showed this approach greatly reduced the total time and effort required for SRAF placement optimization compared to rule-based method, with better lithographic performance for various layout types when compared to rule-based approach.

In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.

In this work, a potential drawback of simultaneously representing a set of data that contains line-ends, isobar, block structure, and pitch linearity intensity signal using a single representative model have been resolved. In a typical model-OPC procedure, a set of pattern data representative of OPC layout is calibrated using a single representative model, and this model may be a scalar or a vector at constant threshold or variable threshold. Nevertheless, traditional methodology treats a set of pattern data as a whole believing that it provides a best representation of a more complicated environment. In this study, pattern type specific models are used to perform optical proximity correction. This multi-model approach distinguishes each pattern type and specified pitch range a priori to obtaining intensity signal by checking for neighboring segment. Based on this search result, its segment is classified into a pattern type and sub-group, and then, pattern specific models are applied. This approach provides improved calibration result for strong off-axis illumination and optical proximity correction result which will be difficult to achieve with a single representative model.

This paper presents ILT masks written by a DUV laser writer and a VSB e-beam writer, and their corresponding wafer print results. ILT mathematically determine the mask features that produce the desired on-wafer results. ILT-generated masks sometimes are non-intuitive, and different than those produced by past approaches; therefore, their manufacturability must be understood. In this study ILT was applied to create binary chrome-on-glass (CoG) masks with feature sizes ranging from 130 nm to 45 nm (at the wafer scale). The masks were written with both DUV laser (AMAT Alta 4300) and electron beam (JEOL JBX-9000) pattern generators. Wafers were then printed on a 193 nm scanner (ASML 1400, NA = 0.75). Mask image quality and wafer image quality (SEM micrographs and focus-exposure CD performance) were collected. In addition, it was also demonstrated that ILT has the capability to tune the mask complexity by constraining fracture figure size and the minimum mask feature/space.

Optical Proximity Correction (OPC) improves image fidelity by adding and subtracting small enhancement shapes from the original pattern data. Although the presence of these small shapes improves the final wafer image quality, it causes an increase in total figure count, longer fracture processing time, and the introduction of sliver figures. These undesirable artifacts can have a negative impact on the mask write time and mask image quality. In this paper we outline alternative OPC treatments which reduce the additional figures produced, and make the layout configurations friendlier to the subsequent mask fabrication phase. These include the alignment of neighboring small shapes during the OPC operation, and the preservation of jog alignment during the biasing phase. Illustrations of example pattern data, and improvement results in terms of figure counts are described.

Matrix Semiconductor have successfully implemented chrome-less phase shifting mask to their 0.13μm half pitch, 3D memory circuit process using 0.7NA KrF photolithography. The K1 factor is 0.37. OPC for post structures at the edge of memory array presents a special challenge for 3-D memory circuits. As 3-D memory circuits are stacked vertically, the topography also accumulates to the top of memory layers, thus resulting in reduced process margin due to "peeling off" of edge posts. Ruled based and model based OPC for edge posts are studied in this paper. A simple ruled based OPC is developed to compensate the size difference between the posts at array center and the ones at array edge. A manufacturing oriented OPC strategy is used to gain optimum process windows. The wafer printing results from ruled based OPC are compared to the model prediction from commercial lithography software. Discrepancy between wafer printing results and model prediction using thin film mask approximation is reported. A new model based OPC method for chrome-less PSM in the application to post structures is proposed from this study.

Sophisticated designs of the pupil illumination fill of scanners and steppers permit considerable improvements of the resolution and the quality of the optical projection for certain critical patterns. However, the mask layout can have quite different requirements for the resolution as well as the shape of the critical patterns in the two spatial directions. For instance, typical DRAM designs have one orientation with much higher requirements than the other orientation. This asymmetry can be accounted for with a corresponding pupil fill that has a reduced symmetry as well. It is for example possible to combine high resolution and high contrast of the most critical pattern in one spatial orientation at the cost of the other orientation. Unfortunately, this leads to an asymmetric source distribution with x-y dependent optical proximity effects. Therefore the transfer of one and the same pattern from the mask to the wafer will differ if this pattern is rotated by 90 degrees. But fortunately, this anisotropic mapping can be compensated by applying an appropriate optical proximity correction (OPC) which is anisotropic as well. In the current work, we measure on silicon the orientation dependent proximity effect for a customized and strongly asymmetric pupil illumination fill design. With this input data, we build a lithography simulation model which is able to reproduce this anisotropy well. We further perform full chip anisotropic OPC and present the actual success of this resolution enhancement technique with various measurement results and printed wafer images. We also discuss the challenges and problems of this method.

Maskless Lithography (ML2) is again being considered for use in mainstream CMOS IC manufacturing. Sessions at technical conferences are being devoted to ML2. A multitude of new companies have been formed in the last several years to apply new concepts to breaking the throughput barrier that has in the past prevented ML2 from achieving the cost and cycle time performance necessary to become economically viable, except in rare cases. Has Maskless Lithography's (we used to call it "Direct Write Lithography") time really come? If so, what is the expected impact on the mask manufacturer and does it matter? The lithography tools used today in mask manufacturing are similar in concept to ML2 except for scale, both in throughput and feature size. These mask tools produce highly accurate lithographic images directly from electronic pattern files, perform multi-layer overlay, and mix-n-match across multiple tools, tool types and sites. Mask manufacturers are already accustomed to the ultimate low volume - one substrate per design layer. In order to achieve the economically required throughput, proposed ML2 systems eliminate or greatly reduce some of the functions that are the source of the mask writer's accuracy. Can these ML2 systems meet the demanding lithographic requirements without these functions? ML2 may eliminate the reticle but many of the processes and procedures performed today by the mask manufacturer are still required. Examples include the increasingly complex mask data preparation step and the verification performed to ensure that the pattern on the reticle is accurately representing the design intent. The error sources that are fixed on a reticle are variable with time on an ML2 system. It has been proposed that if ML2 is successful it will become uneconomical to be in the mask business - that ML2, by taking the high profit masks will take all profitability out of mask manufacturing and thereby endanger the entire semiconductor industry. Others suggest that a successful ML2 system solves the mask cost issue and thereby reduces the need and attractiveness of ML2. Are these concerns valid? In this paper we will present a perspective on maskless lithography from the considerable "direct write" experience of a mask manufacturer. We will examine the various business models proposed for ML2 insertion as well as the key technical challenges to achieving simultaneously the throughput and the lithographic quality necessary to become economically viable. We will consider the question of the economic viability of the mask industry in a post-ML2 world and will propose possible models where the mask industry can meaningfully participate.

Many people in the semiconductor industry bemoan the high costs of masks and view mask cost as one of the significant barriers to bringing new chip designs to market. All that is needed is a viable maskless technology and the problem will go away. Numerous sites around the world are working on maskless lithography but inevitably, the question asked is "Wouldn't a one wafer per hour maskless tool make a really good mask writer?" Of course, the answer is yes, the hesitation you hear in the answer isn't based on technology concerns, it's financial. The industry needs maskless lithography because mask costs are too high. Mask costs are too high because mask pattern generators (PG's) are slow and expensive. If mask PG's become much faster, mask costs go down, the maskless market goes away and the PG supplier is faced with an even smaller tool demand from the mask shops. Technical success becomes financial suicide - or does it? In this paper we will present the results of a model that examines some of the consequences of introducing high throughput maskless pattern generation. Specific features in the model include tool throughput for masks and wafers, market segmentation by node for masks and wafers and mask cost as an entry barrier to new chip designs. How does the availability of low cost masks and maskless tools affect the industries tool makeup and what is the ultimate potential market for high throughput maskless pattern generators?

Focus on Design for Manufacturing (DFM) in semiconductor device design has increased as semiconductor manufacturing technology has become more complex. Many of the techniques developed to improve wafer yield and manufacturability can also be applied to the photomask manufacturing process. For example, for the last several technology nodes, semiconductor manufacturers have known that pattern density and uniformity can have significant impact on wafer processes such as etching and chemical mechanical polishing. Photomask manufacturing can also be impacted by pattern density and its uniformity. Some of these DFM practices can be beneficial if applied directly to photomask manufacturing while some of them can make photomask manufacturing significantly more difficult. Optical proximity correction (OPC), which involves convoluting the design shape to account for optical, physical and chemical processes, is increasingly required to support advanced lithography; some of the operational parameters of the OPC, such as the fragmentation run length, challenge mask resolution capability, image fidelity, defect inspection, mask repair, and dimensional metrology of photomasks. Sub-resolution assist features (SRAFs), which are utilized to create robust wafer lithography are often the most challenging mask features to create. The size and placement of SRAFs on photomasks are factors that impact photomask manufacturability in terms of image resolution, inspection, and dispositioning criteria. As OPC and other DFM processes become more widely deployed in an effort to make robust wafer manufacturing processes, the photomask maker needs to be involved to evaluate the implications to photomask manufacturing and assist in optimizing these DFM procedures to maximally benefit both the photomask and semiconductor manufacturing processes.

The extension of optical projection lithography through immersion to patterning features with half pitch ⩽65 nm is placing greater demands on the mask. Strong resolution enhancement techniques (RETs), such as embedded and alternating phase shift masks and complex model-based optical proximity correction, are required to compensate for diffraction and limited depth of focus (DOF). To fabricate these masks, many new or upgraded tools are required to write patterns, measure feature sizes and placement, inspect for defects, review defect printability and repair defects on these masks. Beyond the significant technical challenges, suppliers of mask fabrication equipment face the challenge of being profitable in the small market for mask equipment while encountering significant R&D expenses to bring new generations of mask fabrication equipment to market. The total available market for patterned masks is estimated to be $2.5B to $2.9B per year. The patterned mask market is about 20% of the market size for lithography equipment and materials. The total available market for mask-making equipment is estimated to be about $800M per year. The largest R&D affordability issue arises for the makers of equipment for fabricating masks where total available sales are typically less than ten units per year. SEMATECH has used discounted cash flow models to predict the affordable R&D while maintaining industry accepted internal rates of return. The results have been compared to estimates of the total R&D cost to bring a new generation of mask equipment to market for various types of tools. The analysis revealed that affordability of the required R&D is a significant problem for many suppliers of mask-making equipment. Consortia such as SEMATECH and Selete have played an important role in cost sharing selected mask equipment and material development projects. Governments in the United States, in Europe and in Japan have also helped equipment suppliers with support for R&D. This paper summarizes the challenging business model for mask equipment suppliers and highlight government support for mask equipment and materials development.

An informal survey conducted with key customers by Photronics indicates that the time gap between technology nodes has accelerated in recent years. Previously the cycle was three years. However, between 130nm and 90nm there was less than a 2 year gap, and between 90nm and 65nm a 1.5 year gap exists. As a result, the technical challenges have increased substantially. In addition, mask costs are rising exponentially due to high capital equipment cost, a shrinking customer base, long write times and increased applications of 193nm EAPSM or AAPSM. Collaboration among EDA companies, mask houses and wafer manufacturers is now more important than ever. This paper will explore avenues for reducing mask costs, mainly in the areas of: write-time reduction through design for manufacturing (DFM), and yield improvement through specification relaxation. Our study conducted through layout vertex modeling suggests that a simple design shape such as a square versus a circle or an angled structure helps reduce shot count and write time. Shot count reduction through mask layout optimization, and advancement in new generation E-beam writers can reduce write time up to 65%. An advanced laser writer can produce those less critical E-beam layers in less than half the time of an e-beam writer. Additionally, the emerging imprint lithography brings new life and new challenges to the photomask industry with applications in many fields outside of the semiconductor industry. As immersion lithography is introduced for 45nm device production, polarization and MEEF effects due to the mask will become severe. Larger magnification not only provides benefits on CD control and MEEF, but also extends the life time of current 90nm/65nm tool sets where 45nm mask sets can be produced at a lower cost.

Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. Different stacks and manufacturing concepts have been published for the fabrication of the reflective EUVL masks. Patterning processes for two different absorber-buffer combinations on top of the reflective multi layer mirror have been developed. A TaN/SiO₂ absorber-buffer stack was provided by supplier A and TaBN/Cr by supplier B. In addition both absorbers were covered by an anti reflective coating (ARC) layer. An e-beam patterned 300nm thick film of Fuji FEP171 was used as resist mask. We optimized the etching processes for maximum selectivities between absorber, buffer and capping layers on the one hand and rectangular profiles and low etch bias on the other hand. While both TaN based absorbers have been dry etched in an UNAXIS mask etcher III, wet and dry etch steps have been evaluated for the two different buffer layers. The minimum feature size of lines and holes in our test designs was 100nm. After freezing the processes a proximity correction was determined considering both, the influence of electron scattering due to e-beam exposure and the influence of the patterning steps. Due to the correction an outstanding linearity and iso/dense bias on different test designs was achieved. Various masks for printing experiments at the small-field Micro Exposure Tool (MET) in Berkeley and the fabrication of the ASML α-tool setup mask within the European MEDEA⁺ EXTUMASK project were done using the developed processes. Finally, we will compare and discuss the results of the two stack approaches.

We have developed and characterized a stack of TaN (absorber) and TaON (ARC) using reactive magnetron sputtering method. Two DOE (design of experiments) were performed with varying gas and power parameters and their effects on the various film parameters are discussed. We characterized the stress, uniformity, reflectivity (for defect inspection and EUV wavelengths), defect adders, and etch performance. Film property characterization was performed with AFM, Optical reflectance measurement tool, Particle inspection tool and profilometer. Optimized film stack met or exceeded ITRS guideline for EUV lithography mask with film stress less than 200MPa, inspection wavelength reflectivity at 9%, and thickness uniformity less than 5%. Defect adder number (< 0.5 / cm²) was a strong function of underlying film surface roughness and cleanliness of surface as well as deposition parameters.

Key features are presented of the RIM-13 reticle imaging microscope developed for actinic aerial image monitoring of blank and patterned EUV reticles. Details of the opto-mechanical design, module layout, major subsystems including the EUV source and performance of the tool are presented.

An initial Nanoimprint template manufacturing process using a state-of-the-art mask front end line has been developed. The process flow is based on conventional 6025 photomask blanks and known basic process steps for chrome and quartz etching. While these etching processes have been slightly adapted, a comprehensive investigation of chemically amplified resists for this purpose was done. We were able to identify a pre-commercial pCAR enabling to approach the 50nm dense line resolution using the Leica SB350 variable shaped beam e-beam writer. We characterized profile, CD-linearity, CD-uniformity and placement accuracy of the nanoimprint templates. The final imprinting of different pattern proved the applicability of the manufactured stamps for the nanoimprint technology.

At SPIE Microlithography 2005, the concept of direct imprinting of dielectric material for dual damascene processing and its benefits was introduced ¹. Manufacturing a nano-imprint template with multi-tier 3-D structures presents a unique set of challenges. The main issues are patterning two different mask layers with good overlay and etch depth control into the quartz at each step on the same substrate. This work describes the tools and processes used to build these types of structures in a commercial photomask shop. The results of using a template with two levels of patterning to imprint dual damascene 3-D structures will also be presented.

As lithography pushes to smaller and smaller features under the guidance of Moore's Law, patterned features smaller than the wavelength of light must be routinely manufactured. Lithographic yield in this domain is directly improved with the application of OPC (Optical and Process Correction) to the pattern data. Such corrections generally assume that the mask can reproduce these features exactly. The Mask Error Enhancement Factor (MEEF) serves to amplify mask errors, and can reduce the benefits of OPC in some circumstances. In this paper, we present the characterization of the MEEF for 65nm technology attenuated phase shift mask to figure out how to better set mask specs from an OPC perspective and how to measure the masks relative to these specs and try to figure out new ways to reduce model sensitivity to mask deviations for metal level.

As semiconductor process technology moves down below 90nm and 65nm, more and more wafer fabs are starting to apply 193nm CPL (Chromeless Phase Lithography) technology as the main lithography strategy for their most critical layers. However the 3D pattern profile is another critical factor, which affects image intensity and final process window. Since 193nm CPL is a relatively new technology in the semiconductor industry, it is important for us to understand the key mask specifications of 193nm CPL and their impact on wafer-level imaging. In this paper, we will study the effects of sidewall angle on process window and wafer CD using 193nm CPL masks in a 300mm wafer manufacturing environment. We begin our experiment by making several special 193nm CPL masks. These masks have been specially designed with different sidewall angles (SWA) with phase of 180 degrees. The sidewall angle spread represents approximately 10 degrees. We use specially designed test patterns that are compatible at the 65nm technology node. In our experiment, we first study the correlation between AFM (atomic force microscope)-determined profile angle and lithographic process behavior. In addition, simulation was also used to predict the impact of 3D profile on process performance. All lithographic experiments were performed on 300mm wafers using a high NA ASML 193nm scanner and high contrast resist. In this study, we have focused on the impact of sidewall angle on wafer process performance by comparing the wafer CD and pattern profile through focus. In order to establish more effective specifications of angle control in 193nm CPL between mask shop and wafer fabs, all AFM, wafer CD, and simulation results will be compared and correlated.

Design tools exploit design hierarchy for speed, efficiency and reuse. Conventional optical proximity correction (OPC) tools process design layouts in a sequential mode layer by layer to ensure stability of the resolution enhancement technology (RET) corrections. A typical sub-100 nm design layout is very large and OPC expands the data volume significantly. The large data volumes and long run-times associated with conventional OPC are becoming critical bottlenecks for manufacturing turn-around time. In a full-chip layout comprised of a library of cells, a cell may be instantiated thousands of times. Aprio's incremental OPC technology applies a design-like methodology that exploits the hierarchical structure of the layout. OPC is applied once per master cell rather than once per cell placement. The master cells are reused and can be instantiated across different designs. These pre-OPC'ed cells are reconverged or "stitched" together at their interacting halo areas to build up proximity-corrected, hierarchical layouts. This alleviates the need to run OPC sequentially on multiple designs where the master cell is instantiated, thus leading to significantly reduced run-time and data size. We are able to extend this to applications such as manufacturing engineering change order (ECO) handling and design re- spins without the need to rerun the entire OPC layout. Since our incremental technology can "stitch" together previously OPC corrected areas and cells, we are able to combine less complex areas along with "critical-care" areas leading to a more robust final layout that is optimally designed for manufacturing.

In recent years, more burden is placed on OPC(Optical Proximity effect Correction) and ORC(Optical Rule Check) like never before due to low process margin caused by adoption of "Low K1" technology on lithography process. Normally, chip is composed of cell, core and periphery regions. Each of these regions has different characteristics patterning wise but usually the region with high density has much more chance for pinch, bridge or killing error and also has small process window. So verification of OPCed data must be highly accurate with fast operation speed. In this paper we developed full chip based ORC(Optical Rule Check)which satisfies both need, accuracy and speed. The result of pinch, bridge and small process window verification of Hybrid ORC will be shown followed by comparison of rule and model ORC methods.

MEEF (Mask Error Enhancement Factor) has become a critical factor in CD uniformity control since optical lithography process moved to sub-resolution era. A lot of studies have been done by quantifying the impact of the mask CD (Critical Dimension) errors on the wafer CD errors^1-2. However, the benefits from those studies were restricted only to small pattern areas of the full-chip data due to long simulation time. As fast turn around time can be achieved for the complicated verifications on very large data by linearly scalable distributed processing technology, model-based lithography verification becomes feasible for various types of applications such as post mask synthesis data sign off for mask tape out in production and lithography process development with full-chip data^3,4,5. In this study, we introduced two useful methodologies for the full-chip level verification of mask error impact on wafer lithography patterning process. One methodology is to check MEEF distribution in addition to CD distribution through process window, which can be used for RET/OPC optimization at R&D stage. The other is to check mask error sensitivity on potential pinch and bridge hotspots through lithography process variation, where the outputs can be passed on to Mask CD metrology to add CD measurements on those hotspot locations. Two different OPC data were compared using the two methodologies in this study.

We propose a combined cell stencil (CCS), a shot reduction method, for character projection lithography (CPL). Electron Beam Direct Writing (EBDW) has been focused on the maskless chip fabrications, in terms both of quick turn-around-time and chip fabrication cost reduction for the nano-meter VLSI processes. EDBW, however, suffers from less throughput performance than the conventional optical lithography. CPL, which employs stencil masks to utilize the pattern beam, has been reported to reduce numbers of shots to 1/10 to 1/15 compared with the conventional variable shaped beam projection. The conventional cell stencil consists of a single cell layout pattern. The proposed CCS consists of two or more cell layouts, which are frequently connected to each other in netlists. We find frequently connected cell pairs in netlists to form new stencil patterns, as CCSes. Assuming that the frequently connected cells are usually placed close to each other on layout, timing closure will not be seriously degraded with this method. We evaluated the proposed method in terms of numbers of shots in layout patterns generated from place and route tools, whose netlists are replaced with the CCSes from the original cells, which is completely compatible with the conventional cell-based design flow. We applied the proposed method to a microprocessor design and demonstrated 22.4% shots reduction with 4.4% area increase compared with the previously reported shot reduction method for CPL. We also carried out IWLS (International Workshop on Logic Synthesis) benchmarks to show the reusability of the generated CCS stencil masks.

In the photo-lithography process, a mask is one of the most important items because its imperfection induces the variation of critical dimension (CD) and becomes the source of the CD error on the wafer. The CD error amplification is denoted by using Mask Error Enhancement Factor (MEEF)^(1,2) and related to the photo-lithography process. Nowadays MEEF increases conspicuously as the device shrinks so fast. Therefore the mean-to-target (MTT) and the uniformity of the mask CD are very important factors to reduce the effect of high MEEF. In general, the process constant k₁ factor has been cited to denote the capability of the photo process for a certain resolution. However MEEF can describe the process difficulty well because it depends on the layout design and the process conditions although the designed patterns have the same design rule. In this study the MEEFs of sub-80nm DRAM patterns⁽³⁾ are discussed with the process constant k₁, MTT and the mask CD uniformity. And then the results are compared with the simulation and the wafer process data. Considering the mask specification calculated from the wafer specification and MEEF, the photo tool and process upgrade is necessary to reduce MEEF and to have the mask fabrication tolerance.

Defect disposition and qualification with stepper simulating AIMS^TM tools on advanced masks of the 90 nm node and below is key to match the customer's expectations for "defect free" masks, i.e. masks containing only nonprinting design variations. For defect dispositioning usually printability studies are carried out using the same illumination settings at the AIMS^TM tool as later on at the steppers in the wafer fab. These studies then establish an AIMS^TM criterion (e.g., CD variation or transmission deviation) a structure deviation must not exceed. For ever more advanced technologies the accessible process window gets smaller and thus more and more complex apertures have to be used to allow for a still suitable contrast and reliable printing of the patterns. This results in more time-consuming printability studies and tighter AIMS^TM specs. Simulations of the printing of mask defects could potentially help to decrease the amount of time for printability studies and also the time for defect disposition in the production. However, usually simulations in their first approximation do not account for effects such as flare, aberrations or illumination inhomogeneities of the AIMS^TM tool. This makes it difficult to derive the AIMS^TM criterion by simulations. In this paper we show that a homogeneous aperture illumination is crucial for the image contrast and the defect disposition. We present a method to characterize the pupil illumination and investigate the impact of illumination inhomogeneities on various structures and their orientation employing two different aperture types. The experimental results are compared to simulations with both homogeneous illumination and the real illumination distribution. It turns out that for correct simulation predictions on experimental results it is important to provide the correct illumination distribution to the simulations.

In this paper, we evaluated and investigated techniques for performing fast full-chip post-OPC verification using a commercial product platform. A number of databases from several technology nodes, i.e. 0.13um, 0.11um and 90nm are used in the investigation. Although it has proven that for most cases, our OPC technology is robust in general, due to the variety of tape-outs with complicated design styles and technologies, it is difficult to develop a "complete or bullet-proof" OPC algorithm that would cover every possible layout patterns. In the evaluation, among dozens of databases, some OPC databases were found errors by Model-based post-OPC checking, which could cost significantly in manufacturing - reticle, wafer process, and more importantly the production delay. From such a full-chip OPC database verification, we have learned that optimizing OPC models and recipes on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. And, fatal errors (such as pinch or bridge) or poor CD distribution and process-sensitive patterns may still occur. As a result, more than one reticle tape-out cycle is not uncommon to prove models and recipes that approach the center of process for a range of designs. So, we will describe a full-chip pattern-based simulation verification flow serves both OPC model and recipe development as well as post OPC verification after production release of the OPC. Lastly, we will discuss the differentiation of the new pattern-based and conventional edge-based verification tools and summarize the advantages of our new tool and methodology: 1). Accuracy: Superior inspection algorithms, down to 1nm accuracy with the new "pattern based" approach 2). High speed performance: Pattern-centric algorithms to give best full-chip inspection efficiency 3). Powerful analysis capability: Flexible error distribution, grouping, interactive viewing and hierarchical pattern extraction to narrow down to unique patterns/cells.

Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD measurements. However, these measurements are not comprehensive enough, limited to a very few layout features. It is desirable to confirm lithographic process window robustly, for all the cell design features of interest, to ensure full functionality of the cell. In this work, we propose for the first time to focus on the electrical deliverables after ILT pattern quality has been initially verified by SEM visual inspection. We designed an electrically measurable SRAM structure for a 65 nm process, to extract device and interconnect parameters depending on the lithographic process conditions, as a means to compare pattern quality of the conventional mask creation technique, Optical Proximity Correction (OPC) with ILT. We present the drawn layout, the masks created by the two technologies, and the corresponding image simulation and silicon pattern.

In this paper we present unintuitive patterns generated by inverse lithography technology. We show examples of contact hole masks designed with ILT that enjoy larger process windows than OPC. We also show variations in ILT-generated masks as the pitch of the contact hole array changes. In another example, we show poly masks designed for better process window to be substantially different from poly masks designed for better fidelity at nominal exposure-defocus (ED) condition. The mask with better fidelity has broken lines in comparison to the original layout. In a third example, we show deep trench mask patterns designed with ILT that, at first glance, bear no resemblance to the original layout, yet provide high fidelity in optical images. These patterns, although complex at first sight, can be generated in substantially simpler form with proper constraints without losing the spirit of ILT masks.

To perform a thorough source optimization during process development is becoming more critical as we move to leading edge-technology nodes. With each new node the acceptable process margin continues to shrink as a result of lowering k1 factors. This drives the need for thorough source optimization prior to locking down a process in order to attain the maximum common depth of focus (DOF) the process will allow. Optical proximity correction (OPC) has become a process-enabling tool in lithography by providing a common process window for structures that would otherwise not have overlapping windows. But what effect does this have on the source optimization? With the introduction of immersion lithography there is yet another parameter, namely source polarization, that may need to be included in an illumination optimization process. This paper explored the effect polarization and OPC have on illumination optimization. The Calibre ILO (Illumination Optimization) tool was used to perform the illumination optimization and provided plots of DOF vs. various parametric illumination settings. This was used to screen the various illumination settings for the one with optimum process margins. The resulting illumination conditions were then implemented and analyzed at a full chip level. Based on these results, a conclusion was made on the impact source polarization and OPC would have on the illumination optimization process.

The mask error enhancement factor (MEEF) minimization is much emphasized due to the reduction of the device technology node. The MEEF is defined as how mask critical dimension (CD) errors are translated into wafer CD errors. We found that the pattern density had influenced the MEEF and the MEEF changed with the pattern density variation. We also tried to obtain the 90 nm CD value with optimized diffusion length of the chemically amplified resist. It turned out that a very small diffusion length should be used to get the desired 90 nm line width with 193 nm. We used line and space (L/S) dense bars, 3 L/S bars only and isolated line pattern for the pattern density dependency and to obtain different MEEFs. In order to determine the MEEF by the various pattern densities, a commercial simulation tool, Solid-E, was used. We could obtain the minimum MEEF values for the different pattern densities by using this procedure.

With the advent of the first immersion and hyper-NA exposure tools, source polarization quality will become a hot topic. At these oblique incident angles, unintentional source polarization could result in the intensity loss of diffraction orders possibly inducing resolution or process window loss. Measuring source polarization error on a production lithographic exposure tool is very cumbersome, but it is possible to reverse engineer any source error similarly to what has been accomplished with intensity error. As noted in the intensity maps from the source illumination, it is not safe to assume an ideal or binary source map, so model fitness is improved by emulating the real error. Likewise, by varying the source polarization types (TE, TM, Linear X and Linear Y) and ratios to obtain improved model fitness, one could deduce the residual source polarization error. This paper will show the resolution and process window gain from utilizing source polarization in immersion lithography. It will include a technique demonstrating how to extract source polarization error from empirical data using the Calibre model and will document the modeling inaccuracy from this error.

As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.

The contact hole imaging is a very challenge task for the optical lithography process during IC manufacturing. Lots of RETs were proposed to improve the contrast of small opening hole. Scattering Bar (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1 contact imaging. In this study, an effective model-based SB OPC based on IML technology is implemented for contact layer at 90nm, 65nm, and 45nm nodes. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. Then, we selected the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, the model-based SB OPC is performed. Next, model OPC can be applied with the presence of SB for the entire chip. It is important to note that, for patterning at k1 near 0.35 or below, it may be necessary to include 3D mask effects with a high NA OPC model. With enhanced DOF by IML and immersion process, the low k1 production worthy contact process is feasible.

Alternating Aperture Phase Shifting Mask (Alt-APSM) has been expected as one of the practical techniques for 45nm node ArF lithography. We have already discussed and proposed the Single trench with undercut (UC) and bias structure is the primary candidate for 65nm node Alt-APSM structure. In fact, we have selected this structure as a standard in production for 65nm node Alt-PSM. For the 45nm node, according to the design shrinkage, mask rule such as MRC which specify minimum chrome CD between 0 and pi degree apertures and etc. is getting tighter. So, we need to consider about single trench with no undercut and bias structure. Such two types of structure are the candidates for 45nm node Alt-APSM. Exposure conditions will be considered as 0.9 or higher NA and the immersion technology as well. In this work, we will discuss about 45nm node Alt-PSM structure in terms of lithographic performance by using 3D rigorous optical simulation software. Two types of structure, single trench with UC and bias, and single trench with No UC and bias are compared. We examined the following items to find optimum Alt-PSM structure, 0/pi space bias to minimize CD difference at the wafer, quartz depth to optimize effective phase and optical proximity correction (OPC) to adjust printed line CD in through pitch condition. Wafer printing performance will be evaluated by the stability of line CD and 0-pi CD difference, contrast, NILS, phase angles, MEEF, ED-window and gate position shift.

Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k₁, e.g. k₁<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k₁<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Chemically amplified resists, CAR, and 50kV e-beam writers have been applied for the most advance mask manufacturing. To fulfill the requirement of 65nm generation a good performance resist played an important role. In this work, two advanced positive and negative CAR resist has been evaluated for 65nm photomask process with a 50kV e-beam pattern generator in an advanced process line. For 65nm node not only the resolution is needed to be improved but also the cirtical dimension(CD) control will be more critical than previous generation. So the evaluation is focus on the CD performance, resolution, profile, e-beam sensitivity, line edge roughness(LER), etc.

Excessive dark loss has been observed along the edge nearest the lid of aged chemically amplified resist blanks, which was traced to organic acid contamination evolving from the acrylic plastic lid of the shipping box. Thermal Gravimetric Analysis (TGA) combined with Fourier Transform Infrared Spectroscopy (FTIR) of the shipping box lid material have proven useful in identifying that organic acid evolves from the plastic at 110°C. An alternative plastic shipping material offered by the supplier was tested with the same analysis technique and no organic acid was evolved during the test. To accelerate the aging effect, both lid materials were baked in an oven for 4 days, and no excessive dark loss was observed with the new shipping material. An evaluation with chemically amplified resist comparing storage in the original shipping materials at ambient conditions vs. storage in dry nitrogen demonstrate that nitrogen storage improves, but does not eliminate, the excessive dark loss from the original plastic lid material.

In recent years, organic compounds have been clarified as one of major root causes of the haze, and carbon and amine components are major of them to organize. Therefore, both two should be controlled simultaneously for preventing haze defects on photomask. It is well known that UV/O₃ treatment has a strong efficiency of removing organic matters¹. For that reason, we have inserted it into our cleaning process, especially for EA.PSMS. And the surface variation of mask, after UV/O₃ treatment, has been confirmed by the change of surface free energy on it. And organic matters remaining on mask surface have been identified by Gas Chromatography Mass Spectrometry (GC MS) with two different sample preparation methods: Thermal Desorption (TD) and direct extraction. As a result of UV/O₃ treatment, we confirmed that it has an excellent removing efficiency of aromatic compounds and semi-volatile organics on mask surface. Finally, through the haze accelerating tests, we have known that conventional SPM/SC-1 cleaning with UV/ O₃ treatment has been having a much higher threshold energy value in terms of causing haze defects on masks about 20 times higher than that of the cleaning with just SPM/SC-1.

Today, haze and crystal growth on the reticle surface are still a primary concern of the microlithography industry. The crystals limit the reticle usage as they result in printable defects on the wafers. Numerous studies have been presented so far. The general belief is that different root causes can lead to crystal growth and haze formation, among them the contaminants on the mask surface from the clean processes. In this paper we are investigating the potential of sulfate free clean processes based on ozonated and hydrogen water for the next generation of photomasks. Key parameters such as cleaning efficiency, as well as the impact of the chemistry on the mask optical properties will be presented. The potential of the chemistry will be discussed and compared to the standard cleaning processes.

Contaminants and residues on the mask surface are still a concern to the Microlithography industry as they influence the reticle printing properties. It is conceivable that this effect will worsen as the industry moves toward smaller nodes for the next generation lithography, i.e. 193nm immersion and/or EUV. The AUV5500 (advanced UV-cleaning and inspection) tool provides the possibility to investigate the effect of mask contaminants from transmission and reflection measurements in the spectral range 145nm to 270nm, and to clean the mask surface as well. In this paper, we are investigating the change of optical properties with organic contaminants on mask features and the ability to clean the surface to its original optical properties. At first we discuss the behavior of the 193nm illumination of the features on the mask properties. Then, with the help of a controlled contamination method to pollute the surface, we investigate the influence of the contaminant on the features on the photomask optical properties. The impact of the contaminant on AIMS data will be discussed as well.

Cleaning becomes increasing important and challenging as feature sizes continue to shrink. Many methods and strategies have been explored to reduce particle defects and ion haze that destroy yield on pelliclized reticles. A successful cleaning method must balance reductions of particles and haze while imposing minimal changes to the transmissivity of the chrome stack, to exposed quartz and to the phase shift of molybdenum silicide surfaces. This paper focuses on the inclusion of many previously explored cleaning methods working in concert within a single reticle cleaning tool. We present our findings on elimination of particles with minimum impact on reflectivity and phase angle. We test the collective effects of Ozonated Water (O3W) and final cleaning methods that employ ammonia hydroxide and hydrogen water. These methods are presented within the context of spin cleaning applications.

A great deal of work has been done on identifying the sources of reticle haze. Researchers have sited haze contributions from the atmosphere, from pellicle, pellicle adhesive and from sulfate residuals left by mask cleaning. Residual sulfates from otherwise high performance cleaning processes can range from 30 ppb and up. This paper focuses on final clean methods within a single track tool that leave concentrations of ion residues approaching 1 ppb. We compare different spin processes which use ozonated water and ultra dilute ammonia and hydrogen water through a megasonic head. Other sources of haze producing ions may remain but eliminating contributions from the final cleaning process opens a productive path to higher yield with 65 and 45 nm design rules.

Haze and other progressive reticle defects have been known in the semiconductor industry for more than a decade [1]. Extensive research and experiments have been carried out to determine the sources and origins of the progressive haze growth, but the true mechanisms of its cause are still under speculation. To minimize the wafer yield loss at Samsung Austin Semiconductor (SAS), we introduced a practical method to control the haze defects in a DRAM manufacturing environment that integrates reticle and wafer inspections, reticle cleaning, and a dose-based and time-based control forecast software system. This development has been proven to be very effective in controlling the haze defects and reducing the related yield loss while still supporting high volume wafer production.

With the use of 193nm lithography, haze growth has increased and become a critical issue for photomask suppliers and wafer fabs. Currently, the industry uses various test methods to measure known contributions to crystal growth, such as ion chromatography of cleaning residues and environmental monitoring in steppers. The understanding of the conditions that create haze is limited to end user photomask lifetime experience, which is gathered under varying environmental conditions. A better method to understand the formation of haze is to create a controlled environment and vary experimental conditions. Once experimental factors are understood, product reliability can be verified through end-user feedback. A custom excimer laser test system capable of 193nm and 248nm wavelengths was built to accelerate haze growth and to better understand haze formation. A photomask is enclosed in a test chamber where the environmental atmosphere and exposure conditions are controlled and monitored throughout testing. The system is used to test various elements important to mask fabrication and use, including materials, mask fabrication processes, and environmental operating conditions. This paper details the investigation of haze performance with commercially available pellicles using controlled environmental conditions and varying exposure parameters, such as pulse rate, energy density, and exposure dose. Using this methodology, the conditions that create haze growth were identified.

Low thermal expansion material (LTEM) substrates were cleaned with recipes developed to clean blank quartz substrates. These recipes were capable of cleaning the LTEM without damaging the LTEM substrate. No effect of etching doped metals in LTEM was observed in these experiments. However, LTEM substrates currently require multiple cleaning cycles to obtain the same removal or cleaning efficiencies as quartz substrates. In addition, no change in the surface roughness or degradation of the backside choromium layer was observed.

The simulation and verification of large layout areas is becoming feasible due to the recent convergence of three factors: The ability of compact models to describe process variations, new advances in design layout representations, provided by efficient formats such as OASIS, and continuous improvement of distributed computing systems. Traditional DRC is limited to describe the problem geometrically. Feature width and spacing used to be the main contributors to failure; however, geometric DRC's are becoming insufficient to assure pattern transfer integrity. For most sub-wavelength processes, neighboring structure effects start to become important and in some cases dominant. This work shows that a model-based verification is better equipped to deal with all the rule exemptions imposed by multiple layout configurations, since neighboring structure configurations are accounted during simulation. Following an existing DRC paradigm, the number of layout verification objects has multiplicative domain size with respect to each of the process variables and their corresponding sampling grid. In other words, assuming three process variables (i.e. exposure, focus and mask bias) the verification domain is of size NxMxL (where N, M and L are the number of simulation points for each process variable). By creating intermediate verification data structures such as pv-Bands the number of measured process objects is reduced to two, representing maximum and minimum displacements. In addition, this work suggests that the total number of simulations needed to bind the design verification space is determined by specific process corners, specifically when those process variations refer to defocus, exposure and mask bias.

Accurately and efficiently verifying the device layout is a crucial step in semiconductor manufacturing. A single missed design violation carries the potential for a disastrous and avoidable yield loss. Typically, design rule checking (DRC) is accomplished by validating drawn layout geometries against pre-determined rules, the specifics of which are derived empirically or from lithographic first principles. These checks are intrinsically rigid, and, taken together, a set of DRC rules only approximate the manufacturable design space in the crudest manner. Process-specific effects are entirely neglected. But for leading-edge technologies, process variations significantly impact the manufacturability of a design, so traditional DRC becomes increasingly difficult to implement, or worse, speciously inaccurate. Fortunately, the rise of Optical Proximity Correction (OPC) has given manufacturers a means to accurately model optical and process effects, and, therefore, an opportunity to introduce this information into the layout validation flow. We demonstrate an enhanced, full-chip DRC technique, which utilizes process models to locate marginal or bad design features and classify them according to severity.

With the ever increasing layout data size due to finer geometries and resolution enhancement techniques such as OPC and PSM, handling several tens of gigabytes of GDSII data is becoming very difficult. While new efficient OASIS format is being proposed to replace it, GDSII is here to stay for next several years. This paper discusses two approaches by which the GDSII data can be handled effectively. Reversible compression will be able to produce original GDSII file bit-by-bit and can produce compression of around 20 times. Irreversible compression can produce functionally equivalent GDSII after decompression.

Many companies are ramping their usage of third party wafer foundries for the manufacture of their integrated circuits. As such, new demands of data management and handoff are required. Maintaining a digital record and designing a digital interface with our foundry partners is critical to optimize the tape out and ramp to manufacturing processes. This paper describes the current development of Agere System's 'Foundry Data eXchange' system, which puts structure and consistency around the design data transfer and tape out process. The system streamlines the tapeout process and yields a consistent platform for all data handling. This will lead to greater efficiency and accuracy, saving time during the data handoff. In addition, the system lays the groundwork for the future application of an electronic data handoff with foundry partners.

Etch dummy features are used in the mask data preparation flow to reduce critical dimension (CD) skew between resist and etch processes and improve the printability of layouts. However, etch dummy rules conflict with SRAF (Sub-Resolution Assist Feature) insertion because each of the two techniques requires specific spacings of poly-to-assist, assist-to-assist, active-to-etch dummy and dummy-to-dummy. In this work, we first present a novel SRAF-aware etch dummy insertion method (SAEDM) which optimizes etch dummy insertion to make the layout more conducive to assist-feature insertion after etch dummy features have been inserted. However, placed standard-cell layouts may not have the ideal whitespace distribution to allow for optimal etch dummy and assist-feature insertions. Since placement of cells can create forbidden pitch violations, the placer must generate assist-correct and etch dummy-correct placements. This can be achieved by intelligent whitespace management in the placer. We describe a novel dynamic programming-based technique for etch-dummy correctness (EtchCorr) which can be combine with the SAEDM in detailed placement of standard-cell designs. Our algorithm is validated on industrial testcases with respect to wafer printability, database complexity and device performance.

As the feature size decreases to 90nm and 65nm, the role of phase shift mask as a RET method becomes more and more important. Although alternating PSM has been one of the possible methods to improve the resolution, however, the difficulty of mask manufacturing prevent us from adopting the technology. One of the main issues is microloading effect including RIE lag, pattern density effect that cause especially the imbalance of phase shifting due to the etch depth difference in the patterns with different CD size and different pitch as the feature size downs to subhalf micron. This leads to the space CD difference with the DOF variation in the wafer image. In this paper, characteristics of RIE lag and other phenomenon were evaluated with the DOE method that included such parameters: source power, bias power and pressure. Etch depth difference was confirmed with AFM measurement and calculated to phase shift angle. Results were analyzed with statistical method and major effects and interaction effects were found.

A binary Cr is widely used material as the top coating on a MoSi HT. Generally, a binary Cr mask has larger GL(Global loading) than a MoSi HT by dry etching process. Now we are using a binary Cr as the masking material for a MoSi HT. So if we want to make a MoSi HT pattern with smaller CD variation, we have to make a smaller CD variation for Cr pattern. Two layers, that is, a metal Cr film and a CrOx film, make a binary Cr. GL is one of the source of a CD variation on a MoSi HT. In our investigation, a binary Cr GL is caused by a metal Cr GL. In order to make a MoSi HT with smaller CD variation, we examined monolayer CrOx film, which has a shorter dry etching time and a smaller GL property. As the result, we conformed the optimized monolayer CrOx film can be used as a good masking material for MoSi HT production. We improved GL by the monolayer CrOx film and we found it has a proper OD(Optical Density) and a excellent electric conductivity on a MoSi HT.

Successful implementation of Extreme Ultraviolet Lithography (EUVL) depends on advancements in many areas, including the quality of the mask and chuck system to control image placement (IP) errors. One source of IP error is the height variations of the patterned mask surface (i.e., its nonflatness). The SEMI EUVL mask and chucking standards (SEMI P37 and SEMI P40) describe stringent requirements for the nonflatness of the mask frontside and backside, and the chucking surfaces. Understanding and characterizing the clamping ability of the electrostatic chuck and the effect on the mask flatness is therefore critical in order to meet these requirements. Legendre polynomials have been identified as an effective and efficient means of representing EUVL mask surface shapes. Finite element (FE) models have been developed to utilize the Legendre coefficients (obtained from measured mask and chuck data) as input data to define the surfaces of the mask and the chuck. The FE models are then used to determine the clamping response of the mask and the resulting flatness of the pattern surface. The sum of the mask thickness nonuniformity and the chuck surface shape has a dominant effect on the flatness of the patterned surface after chucking. The focus of the present research is a comprehensive analysis of the flatness and interaction between the nonflat chuck and the mask. Experiments will be conducted using several sample masks chucked by a slab type electrostatic chuck. Results from the study will support and facilitate the timely development of EUVL mask/chuck systems which meet required specifications.

The mechanical distortion of an EUVL mask from mounting in an exposure tool can be a significant source of wafer-level image placement error. In particular, the presence of debris lodged between the reticle and chuck can cause the mask to experience out-of-plane distortion and in-plane distortion. A thorough understanding of the response of the reticle/particle/chuck system during electrostatic chucking is necessary to predict the resulting effects of such particle contamination on image placement accuracy. In this research, finite element modeling is employed to simulate this response for typical clamping conditions.

The present paper will show an approach for a local and global stress determination by the application of a Leica LMS IPRO II mask registration tool. Changes in placement due to a full or partial layer removal on single materials as well as material stacks with respect to a reference grid were determined. Simulation using finite element modeling was conducted to calculate stress values from the placement information. Finally, an estimate was made of the acceptable stress level for a sample design to meet placement requirements for future lithography nodes.

In EUV lithography, when off-axis incident light illuminates an absorber pattern on a reflective multilayer substrate, the side wall of the pattern facing the illumination reflects and absorbs the light, and the side wall on the opposite side casts a shadow. These effects reduce the energy used to create a printed image on a wafer, thereby lowering the image contrast. In addition, when an absorber pattern has a vertical taper, the taper complicates the reflection, absorption and shadowing characteristics. This paper reports on an investigation of how a vertically tapered absorber pattern influences those characteristics and printability based on an analysis of diffracted rays. The printability results revealed that the taper introduces a new error source, namely, the CD (critical dimension) difference on wafer between parallel and perpendicular incidences. The allowable CD difference was found to determine the latitude in the side-wall angle. Moreover, it was found that a thinner absorber increases both the allowable CD difference and the latitude in the side-wall angle at the same time.

Removal of nano-scale contaminant particles from the photomasks is of critical importance to the implementation of EUV lithography for 32nm node. Megasonic cleaning has traditionally been used for photomask cleaning and extensions to sub 50nm particulates removal is being considered as a pattern damage free cleaning approach. Several mechanisms for removal are believed to be active in megasonic cleaning systems, e.g., cavitation, and acoustic streaming (Eckart, Schlichting, and microstreaming). It is often difficult to separate the effects of these individual mechanisms on contamination removal in a conventional experimental setup. Therefore, a theoretical approach is undertaken in this work with a focus on determining the contribution of acoustic streaming in cleaning process. A continuum model is used to describe the interaction between megasonic waves and a substrate (fused silica) immersed in a fluid (water). The model accounts for the viscous nature of the fluid. We calculate the acoustic vibrational modes of the system. These in turn are used to determine the acoustic streaming forces that lead to Schlichting streaming in a narrow acoustic boundary layer at the substrate/fluid interface. These forces are subsequently used to estimate the streaming velocities that may in turn apply a pressure and drag force on the contaminant particles adhering to the substrate. These effects are calculated as a function of angle of incidence, frequency and intensity of the megasonic wave. The relevance of this study is then discussed in the context of the cleaning efficiency and pattern damage in competing megasonic cleaning technologies, such as immersion, and nozzle-based systems.

Extreme Ultraviolet lithography requires defect free multilayer-coated masks. The defects in multilayer-coated masks originate from several sources including: the incoming substrate, pre-multilayer deposition cleaning, multilayer deposition, and handling processes. A previous study showed the majority of currently detectable defects are contributed by the incoming substrate. The purpose of this study is to understand the ability of multilayer deposition to modulate the size and shape of substrate pits, and to, ultimately, enable us to determine if a defect of a particular size and shape is tolerable, and will result in a non-printable pit after coating. In order to execute a systematic study, pits with controlled sizes and shapes were required. Programmed pit arrays were generated using Focused Ion Beam (FIB). The arrays were designed to contain pits of various widths and depths. The physical size of these pits was measured using Atomic Force Microscope (AFM) and Scanning Electron Microscope (SEM) both before and after multilayer deposition. These programmed pit arrays were also used to probe the sensitivity of a state of the art Lasertec M1350 defect inspection system to defect size and shape both before and after coating. Finally, the results were compared to those from natural pits. The programmed defects generated in this study will also enable further development of defect mitigation by other planarization techniques as well as improving inspection recipes.

The standard silicon (Si) capping layer used for extreme ultra-violet lithography (EUVL) multilayer (ML) mask blanks has some shortcomings, such as low oxidation resistance, low chemical resistance, low etch selectivity in either the SiO₂ buffer layer etch to the capping layer or the absorber etch (e.g., TaN) to the capping layer. These performance and process issues with Si capped ML mask blank will reduce the mask lifetime and require tighter process control during EUVL mask fabrication. Alternative capping materials have been investigated for both EUVL optics and for mask applications.^1-5 It has been initially demonstrated that Ru capping layers have high oxidation resistance and high mask process margin as compared to Si ML cap. In this paper, we will present a detailed evaluation of Ru and ion beam deposited (IBD) diamond-like-carbon (DLC) for EUVL mask application. Performance evaluations of the DLC mask blank capping layer and Ru capping layer were made in the area of reflectivity performance, shelf-life, and EUV exposure stability. It has been shown that EUV exposure induced capping layer change depends upon the exposure conditions. However, we found that as long as the induced relative change in the ML cap material are the same (e.g., the same amount of oxidation), regardless of exposure time and exposure conditions, the resulting reflectivity change is about the same. In the case of the two capping layer materials we evaluated, the capping surface reaction with active oxygen is the primary cause for the reflectivity degradation.

A multibeam confocal inspection (MCI) beta-tool for mask blank defect detection has been developed and widely adopted at several organizations involved in the research and development of low-defect extreme ultraviolet (EUV) mask blanks. There are two important objectives of this tool development project: (1) ensuring that all printable multilayer and substrate defects are detectable at the half-pitch 45-nm technology node and beyond and (2) enabling a metrology standard for acceptance or rejection of mask blanks before further processing such as deposition and patterning. This paper documents the technical challenges and the latest best known methods developed to (1) improve the detection sensitivity of the current MCI tool before the next-generation tool arrives and (2) quantify the detection sensitivity differences and correlate the measurement results of the same mask blank from different MCI tools. Several options are discussed and found to be effective to increase sensitivity. Tool differences are discussed and a calibration standard based on a tool detection model and a confocal imaging model is proposed. This work will result in one of the key methodologies required to ensure the yield of EUV lithography.

Increasing numbers of MEMS, photonic, and integrated circuit manufacturers are investigating the use of Nano-imprint Lithography or Step and Flash Imprint Lithography (SFIL) as a lithography choice for making various devices and products. Their main interests in using these technologies are the lack of aberrations inherent in traditional optical reduction lithography, and the relative low cost of imprint tools. Since imprint templates are at 1X scale, the small sizes of these structures have necessitated the use of high-resolution 50KeV, and 100KeV e-beam lithography tools to build these templates. For MEMS and photonic applications, the structures desired are often circles, arches, and other non-orthogonal shapes. It has long been known that both 50keV, and especially 100keV e-beam lithography tools are extremely accurate, and can produce very high resolution structures, but the trade off is long write times. The main drivers in write time are shot count and stage travel. This work will show how circles and other non-orthogonal shapes can be produced with a 50KeV Variable Shaped Beam (VSB) e-beam lithography system using unique pattern transforms and primitive shapes, while keeping the shot count and write times under control. The quality of shapes replicated into the resist on wafer using an SFIL tool will also be presented.

We describe true continuous-wave (CW), high-power, line-narrowed, deep-ultraviolet (DUV) light sources for the high-resolution metrology tools such as wafer inspection and mask inspection systems. The 198.5-nm CW radiation with 300-mW power has also been achieved by sum-frequency mixing (SFM) of 1064-nm output from a single-frequency Yb³⁺ fiber amplifier with the 244-nm radiation from a frequency-doubled argon-ion laser. The 266-nm CW DUV radiation with 5 W of maximum power has been generated by frequency doubling of 532-nm green laser output. Both sources utilize Brewster-cut CsLiB₆O₁₀ (CLBO) crystal for efficient and stable DUV light generation.

Approaches to verify post-OPC designs for manufacturing have evolved from a number of separate inspection strategies. OPC decorations are verified by design rule or optical rule checkers, the reticle is verified by a reticle inspection system, and the patterned wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with very little data flowing between them. Previously, we reported a new paradigm in design verification, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScan^TM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window, which can be up to twice as large as the process window. DesignScan^TM first simulates the resist images at the nominal conditions (the best focus/exposure-F₀E₀) and compares them to pre-OPC design to detect unacceptable variations. Then it simulates resist images across the focus-exposure window and compares them to the best focus/exposure reference. Defect detection algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window. In this paper we will propose a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. We will also report newly developed 2D defect detectors: line end shortening (LES) and interlayer overlap (ILO). New applications will be discussed and reported; such as, determination of the reticle target CD specification through process window simulation across a range of target CDs by biasing the post-OPC data by a few nanometers in both directions (+ and -). Pattern dependent reticle CD specifications are possible by identifying the weak structures.

Advanced wafer fabs are currently fabricating devices with 90nm and 65nm design rules using 193nm lithography. To meet the challenges at these sub-wavelength technology nodes, mask designers are using a variety of resolution enhancement techniques (RETs) in lithography which require new methods of processing, inspecting and qualifying photomasks. As a result, reticle inspection tools need to be capable of detecting smaller defects on ever tighter critical dimensions and background patterns that are considerably more complicated than before. To meet the challenges of current and future technology nodes, a variety of new inspection modes have been developed on the KLA-Tencor Deep UV TeraScan reticle inspection tool. These new inspection modes include Reflected light (Die-to-Die and Die-to-Database) modes, a Transmitted light Tritone (Die-to-Database) mode for inspecting Embedded Attenuated Phase Shift Masks (EAPSMs) with chrome in the inspection area, as well as a STARlight2 (SL2) mode for contamination detection. The SL2 inspection mode is the natural successor to the STARlight contamination detection algorithm on the previous generation of KLA-Tencor reticle inspection tools. Each of the inspection modes comes with its own set of inspectability and sensitivity capabilities and therefore the selection and/or optimization of a mode can depend upon a number of factors. In this paper we will present the inspection modes that are available on the TeraScan platform and discuss the appropriate use cases for each of the modes, based on reticle type and the intended objectives of the inspection.

In mask fabrication pattern-inspection is a key step. It ensures mask quality is being met according to the customer defect criteria. Tool selection is based on a comparison between customer requirements and tool capabilities. Inspection tools are typically specified by a minimum feature size at which a certain minimum defect size can be achieved. Mask shops on the contrary manufacture masks for a wide range of feature and defect sizes. As a consequence detailed tool characterizations are needed, which go beyond the typical tool specifications. In this paper characterization results for three KLA 576 inspection systems are presented. Defect sensitivity was studied for the pixels named P125 and P90 in combination with the so-called die-to-die (D2D) and die-to-database (D2Db) algorithms using standardized programmed defect masks. The good correlation of the qualification data made modeling of the tool behavior possible. The modeling parameters were used to compare tool-to-tool and plate-to-plate variations as well as specified and actual tool performance. For a variety of mask types, such as Chrome-on-Glass (COG) masks, embedded phase shift masks at a lithography wavelength of 193 nm (EPSM-193), and extreme ultra-violet (EUV) masks, the optical contrast was studied over a wide range of feature sizes. From the resultant data material dependence and image contrast below the minimum feature size was evaluated.

To countermeasure the haze problem on a reticle, we investigated the mask storage environment of wafer manufacturing Fab and mask manufacturing Fab. Through IC (Ion chromatography) and AIM system, we measured the outgas quantities of Fab environment, SMIF pod, mask carrier boxes and pellicle. With the evaluation result, the environmental factors around the production mask do not meet the level of its residual SO₄ ion. We suggested the imminent priority to improve the environment surrounding the production masks. Additionally, we adopted a new process to decrease the SO₄ outgas of pellicle frame up to 90%.

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology also. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications. The advantages on the wafer side for the adoption of imprint lithography is the simplification of processing, reduced capital costs and process control when integrated in the wafer fab. The adoption of imprint reduces the barrier of entry to state of the art resolution for many older existing fabs that cannot spend upwards of 30 million dollars on an immersion I-line cluster. In this paper we will explore not only the technical aspects of imprint lithography, but also the economic impact as well.

In the field, each customer uses their owned designed reticle case as for shipping, storage. To modify the case is so expensive that it is very difficult to improve, especially in time respect. At the blank suppliers, they ship their mask blanks packing into their owned designed multiple shipper, however the market needs single shipper with next generation blanks to prevent from particle and outgas of case material damage. At the mask shops, most of them use MP567 (Trade mark of Dainichi Shoji K.K.) single case which was designed about 15years ago to ship their products to their customers. It is not designed for robot handling, so contamination from manual handling makes reticle damaged. Adhesive tape is also required to seal it, so chemical contamination will be occurred on quartz glass, i.e. haze. At the IC fabs, scanner case such as Nikon, Canon and ASML case is the most common in their process. However these cases are not airtight, so they cannot be handled under class 10000 circumstances. RSP (Reticle SMIF Pod) has a capability of automatic transportation, however it is not airtight case. We develop new mask case named Universal Reticle Pod (URP) at affordable price, airtight and chemical tight so as to be used as shipping, storage and process case. We evaluate it as blanks shipping case, so we would like to report its results.

At the deep Subwavelength process nodes, the use of the aggressive optical proximity correction (OPC) and resolution enhancement techniques (RET) is fostering an exponential increase in output database size causing the CPU time required for mask tape-out to increase significantly. This sets up challenging scenarios for integrated device manufacturers (IDMs), and Foundries. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround for a CMOS process around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes. Unlike silicon processing, masks tape-out time can be decreased by applying a combination of extra computing resources and enhancements in the OPC tool like Fracture Friendly OPC (FFOPC) . Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue. Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl's law. Very few are efficient enough to allow the effective use of 100's of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.

Leading-edge photomask, to which optical proximity correction (OPC) and dummy pattern are applied, almost always has complex patterns. Complex patterns such as "Narrow Space", "Thin Pattern", "Dummy Pattern", "Closely Face-to-Face Heads" of Posi Serifs, "Narrow Waisted Pattern" formed by a Nega Serif, "Jogs", etc. are a factor to complicate photomask manufacturing. Some the problems caused by complex patterns are increase in EB writing time, and decrease in performance of etching and cleaning process caused by Cr peeling and, above all, increase in the inspection time. Patterns whose complexity is beyond the resolution limit of inspection tool are detected as false defects. Therefore, it will greatly take time for the data investigation and re-inspection, etc. for assurance, and this causes congestion of half-finished products. To improve the process efficiency, it is necessary to locate false defects, so that the Do-Not-Inspection-Area(DNIR) or replaced with simpler patterns. In order to locate false defects, it is proposed to apply Mask Rule Check (MRC) to mask data for EB-writing.

Mask data preparation (MDP) for modern mask manufacturing becomes a complex process because many kinds of EB data formats are used in mask makers and EB data files continue to become bigger by the application of RET. Therefore we developed a unified mask pattern data format named "OASIS.VSB¹" and a job deck format named "MALY²" for Variable-Shaped-Beam (VSB) EB writers. OASIS.VSB is the mask pattern data format based on OASIS^{TM 3} (Open Artwork System Interchange Standard) released as a successive format to GDSII by SEMI. We defined restrictions on OASIS for VSB EB writers to input OASIS.VSB data directly to VSB EB writers just like the native EB data. OASIS.VSB specification and MALY specification have been disclosed to the public and will become a SEMI standard in the near future. We started to promote the spread activities of OASIS.VSB and MALY. For practical use of OASIS.VSB and MALY, we are discussing the infrastructure system of MDP processing using OASIS.VSB and MALY with mask makers, VSB EB makers, and device makers. We are also discussing the tools for the infrastructure system with EDA vendors. The infrastructure system will enable TAT, the man-hour, and the cost in MDP to be reduced. In this paper, we propose the plan of the infrastructure system of MDP processing using OASIS.VSB and MALY as an application of OASIS.VSB and MALY.