Statistical analysis of gate CD variation for yield optimization

Juliet Holwill; Jongwook Kye; Yi Zou

doi:10.1117/12.712178

21 March 2007 Statistical analysis of gate CD variation for yield optimization

Juliet Holwill, Jongwook Kye, Yi Zou

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65211P (2007) https://doi.org/10.1117/12.712178
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

A new method for analysis of variation and yield across the whole chip is presented. This method takes into account the stochastic distribution of the input process parameters such as focus and exposure, and performs simulations of the design at the extreme points of the process window. Using a robust model to extrapolate the points within the process window, a full distribution of CDs is produced for each gate, which then is analyzed to provide information about both the individual gate and the variation across the chip.

Citation Download Citation

Juliet Holwill, Jongwook Kye, and Yi Zou "Statistical analysis of gate CD variation for yield optimization", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211P (21 March 2007); https://doi.org/10.1117/12.712178

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