Paper
9 April 2007 Intellectual property protection of IP cores through high-level watermarking
E. Castillo, U. Meyer-Baese, A. García, L. Parrilla, A. Lloris
Author Affiliations +
Abstract
In this paper a watermarking technique for Intellectual Property Protection (IPP) of FPGA-based systems is proposed. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The proposed watermarking technique relies on a procedure that spreads the digital signature in cells of memory structures at Hardware Description Language (HDL) design level, not increasing the area of the system. This signature is preserved through synthesis, placement and routing processes. The technique includes a procedure for signature extraction requiring minimal modifications to the system. Thus, it is possible to detect the ownership rights without interfering the normal operation of the system and providing high invulnerability. To illustrate the properties of the proposed watermarking technique, both protected and unprotected design examples are compared in terms of area and performance. The analysis of the results shows that the area increase is very low while throughput penalization is almost negligible.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
E. Castillo, U. Meyer-Baese, A. García, L. Parrilla, and A. Lloris "Intellectual property protection of IP cores through high-level watermarking", Proc. SPIE 6576, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks V, 657619 (9 April 2007); https://doi.org/10.1117/12.719202
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Cited by 6 scholarly publications.
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KEYWORDS
Digital watermarking

Logic

Discrete wavelet transforms

Intellectual property

Radon

Digital electronics

Field programmable gate arrays

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