VLSI architecture of wavelet transform based on basic lifting elements

Jie Guo; Yunsong Li; Keyan Wang; Chengke Wu

doi:10.1117/12.825222

31 August 2009 VLSI architecture of wavelet transform based on basic lifting elements

Jie Guo, Yunsong Li, Keyan Wang, Chengke Wu

Proceedings Volume 7455, Satellite Data Compression, Communication, and Processing V; 74550E (2009) https://doi.org/10.1117/12.825222
Event: SPIE Optical Engineering + Applications, 2009, San Diego, California, United States

Abstract

In this paper, we propose a lifting architecture based on a basic lifting unit, whose structure performs lifting operations in a repetitive way. By analyzing computational processes in lifting in detail, the reusable Basic Lifting Element (BLE) is presented. The BLE structure is designed and optimized from the viewpoint of hardware implementation. The proposed lifting processor can be executed by arranging BLEs repeatedly. Experimental results show that the proposed architecture can transform any size of tiles with 9/7 filter and 5/3 filter for lossy and lossless compression, respectively. The lifting processor is designed in Verilog HDL and synthesized into Xilinx FPGA, which can run up to 130MHz.

Citation Download Citation

Jie Guo, Yunsong Li, Keyan Wang, and Chengke Wu "VLSI architecture of wavelet transform based on basic lifting elements", Proc. SPIE 7455, Satellite Data Compression, Communication, and Processing V, 74550E (31 August 2009); https://doi.org/10.1117/12.825222

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KEYWORDS

Discrete wavelet transforms

Wavelets

Image compression

Very large scale integration

Clocks

Wavelet transforms

Field programmable gate arrays

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