Paper
14 March 2012 Automated yield enhancements implementation on full 28nm chip: challenges and statistics
Shobhit Malik, Sriram Madhavan, Piyush Pathak, Luigi Capodieci, Ramy Fathy, Ahmad Abdulghany
Author Affiliations +
Abstract
This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Shobhit Malik, Sriram Madhavan, Piyush Pathak, Luigi Capodieci, Ramy Fathy, and Ahmad Abdulghany "Automated yield enhancements implementation on full 28nm chip: challenges and statistics", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270X (14 March 2012); https://doi.org/10.1117/12.915920
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Cited by 3 scholarly publications.
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KEYWORDS
Metals

Design for manufacturing

Manufacturing

Design for manufacturability

Databases

Silicon

Visualization

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