Paper
19 June 2014 Low-complexity multiplierless DCT approximations for low-power HEVC digital IP cores
Sunera C. Kulasekera, Arjuna Madanayake, Renato J. Cintra, Fabio M. Bayer, Uma Potluri
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Abstract
Image and video compression plays a major role in multimedia transmission. Specifically the discrete cosine transform (DCT) is the key tool employed in a vast variety of compression standards such as H.265/HEVC due to its remarkable energy compaction properties. Rapid growth in digital imaging applications, such as multimedia and automatic surveillance that operates with limited bandwidths has led to extensive development of video processing systems. The main objective of this paper is to discuss some DCT approximations equipped with fast algorithms which require minimum addition operations and zero multipliers or bit-shifting operations leading to significant reductions in chip area and power consumption compared to conventional DCT algorithms. We provide complete design details for several k × k, k = 8, 16 blocked 2-D algorithms for DCT computation with video evaluation using HEVC software encoder. Custom digital architectures are proposed, simulated and implemented on Xilinx FPGAs and verified in conjunction with software models.
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Sunera C. Kulasekera, Arjuna Madanayake, Renato J. Cintra, Fabio M. Bayer, and Uma Potluri "Low-complexity multiplierless DCT approximations for low-power HEVC digital IP cores", Proc. SPIE 9089, Geospatial InfoFusion and Video Analytics IV; and Motion Imagery for ISR and Situational Awareness II, 90890W (19 June 2014); https://doi.org/10.1117/12.2050715
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KEYWORDS
Field programmable gate arrays

Image compression

Video

Video compression

Video coding

Multimedia

Computer programming

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