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12 March 2024 Chip-scale hermetic packaging of Si PIC with high-speed electronics and photonics
Mikko Karppinen, Mikko Harjanne, Noora Heinilehto, Jae-Wung Lee, Jyrki Ollila, Jaska Paaso
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Proceedings Volume PC12892, Optical Interconnects XXIV; PC1289205 (2024) https://doi.org/10.1117/12.3006559
Event: SPIE OPTO, 2024, San Francisco, California, United States
Abstract
A chip-scale PIC packaging approach is presented for high-frequency devices. The PIC is attached with a multilayer ceramic interposer and the active devices are hermetically sealed in between the PIC and the interposer. The ceramic interposer part provides high-bandwidth RF lines and integration of the electronic ICs and passives, whereas the active photonic chips can be mounted on the PIC and a fiber array attached for the optical interface. The co-packaging approach was optimized and demonstrated for 3-µm SOI PIC platform integrated with low-temperature co-fired ceramics (LTCC) interposers.
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Mikko Karppinen, Mikko Harjanne, Noora Heinilehto, Jae-Wung Lee, Jyrki Ollila, and Jaska Paaso "Chip-scale hermetic packaging of Si PIC with high-speed electronics and photonics", Proc. SPIE PC12892, Optical Interconnects XXIV, PC1289205 (12 March 2024); https://doi.org/10.1117/12.3006559
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KEYWORDS
Photonic integrated circuits
Packaging
Silicon
Photonics
Ceramics
High speed electronics
Interfaces
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