3.1.

Wafer Preparation

Standard calibration wafers, which have been already reported,⁶ for measuring the I-V characteristics of the incomplete-contact defects were prepared. A schematic cross section of a standard calibration wafer is shown in Fig. 4. Contact plugs with a diameter of 0.16 μm were fabricated on a 300 mm diameter p-type silicon wafer. Defective plugs, in which the contact resistances were precisely controlled, were systematically formed. A thin ${\mathrm{SiO}}_2$ film was formed at the bottom of a defective plug, i.e., an incomplete-contact defect. The resistance of the defects was controlled by the thickness of the thin ${\mathrm{SiO}}_2$ film at the bottom of the contact plug. Three types of wafers, in which the ${\mathrm{SiO}}_2$ thickness of the defects on each wafer was uniformly controlled, were prepared. To precisely control the thickness of the ${\mathrm{SiO}}_2$ film at the bottoms of the contact plugs, these wafers were prepared by the following process. First, normal hole patterns were fabricated on the wafer. A thin ${\mathrm{SiO}}_2$ film, in which the thickness was then precisely controlled, was formed on the normal contact-hole patterns. These wafers were prepared with high-, medium-, and low-resistance defects. Afterwards, the thin ${\mathrm{SiO}}_2$ films on the normal hole-patterns were removed by using a mask fabricated for these standard calibration wafers. The holes were then filled in to complete the contact-plug patterns with systematically formed defects.

Fig. 4

Schematic cross section of a standard calibration wafer.

3.2.

Analytical Results

We analyzed the prepared standard calibration wafers by using cross-sectional TEM and measured their I-V characteristics. Cross-sectional TEM images of the bottoms of the defective plugs are shown in Fig. 5. Uniform ${\mathrm{SiO}}_2$ films were observed at the bottom of the high- and medium-resistance defective plugs. The measured thickness of the ${\mathrm{SiO}}_2$ film at the bottom of the high-resistance defective plug is 8.1 nm, and that of the medium-resistance defective plug is 3.6 nm. The measured thickness of the film at the bottom of a low-resistance defective plug is 4.2 nm, but the bottom shape is different from those of the other images and the film is not as uniform as that in the other images. Accordingly, the film at the bottom of the low-resistance defective plug is thicker than that of the medium-resistance one.

Fig. 5

Cross-sectional TEM images at the bottoms of the defective plugs with three varieties of resistances.

The I-V characteristics of these intentional defects were measured with a nano-prober.⁸ A probe contacting the W-plug surface was biased, and its current was measured. The silicon substrate was connected to the ground. The I-V characteristics between the surface of the W-plug and the silicon substrate were then measured. The resistance of the intentional defects as a function of the differential voltage between the W-plug and the silicon substrate is plotted in Fig. 6. This figure shows that the defect resistance strongly depends on the differential voltage between the plug surfaces and the backside wafer. Accordingly, the defect resistance strongly depends on the charge-up voltage during electron irradiation. The resistance of the high-resistance defect with an 8.1-nm-thick ${\mathrm{SiO}}_2$ film slightly increased, i.e., from ${10}^{12}$ to ${10}^{14}\mathrm{\Omega }$ when the voltage increased from 0 to 8 V because the actual resistance was higher than the measurement limit of the nano-prober in this voltage range. However, the resistance decreased from ${10}^{14}$ to ${10}^{13}\mathrm{\Omega }$ when the voltage increased from 8 to 10 V. Accordingly, the resistance when the voltage ranged from 0 to 8 V was roughly estimated from that when the voltages ranged from 8 to 10 V. The resistance of the medium-resistance defect with a 3.6-nm-thick ${\mathrm{SiO}}_2$ film decreased from ${10}^{13}$ to ${10}^{10}\mathrm{\Omega }$ when the voltage increased from 2 to 5 V. The resistance of the low-resistance plug decreased from ${10}^{13}$ to ${10}^8\mathrm{\Omega }$ when the voltage increased from 0 to 4 V. The resistance of the defective plug can therefore be precisely controlled by the ${\mathrm{SiO}}_2$ film formed at the bottom of the plug. The measured I-V characteristics of the intentional defects formed on these wafers are suitable as typical electrical characteristics of the defective part of the equivalent circuit.

Fig. 6

Resistance of defects measured with a nano-prober as a function of differential voltage between W plug and Si substrate.

SEM images of the intentional defects are shown in Fig. 7. The landing energy of the electron beam was 0.8 keV, and the probe current was 60 pA. The high-resistance defect is easily detected because the image of the defective plug is remarkably dark. The images of the medium- and low-resistance defects are less clear than that of the high-resistance defect. This result shows that the gray scale of a defect plug depends on the resistance of the defect.

Fig. 7

SEM images of an intentional defect on standard calibration wafers.

3.3.

Simulation Results for Standard Calibration Wafer

The gray scales of the SEM images shown in Fig. 7 were compared with the calculated gray scales from the equivalent-circuit model. Figure 8 shows a calibration curve calculated from the equivalent-circuit model considering the measured I-V characteristics of the defects. Probe current $I_p$ was 60 pA. When the landing energy of the electron beam was 0.8 keV, ${\sigma }_{\mathrm{SE}}$ was supposed to be 1.05 and ${\sigma }_{\mathrm{BSE}}$ was supposed to be 0.4; when the landing energy of the electron beam was 1.0 keV, ${\sigma }_{\mathrm{SE}}$ was supposed to be 0.9 and ${\sigma }_{\mathrm{BSE}}$ was supposed to be 0.45. These values of the yields are consistent previously reported ones.^9–11 The voltage contrast was determined from the difference between the total intensity from the normal plugs and that from the defective plug. It was normalized by the difference between the total intensity from the normal plugs and that from the surrounding ${\mathrm{SiO}}_2$ area. The calculated voltage contrasts completely agree with those formed in the SEM images shown in Fig. 7. The differences between the calculated and measured results are less than 1.0% because the charge-up voltage on the defective plug is accurately calculated in consideration of the variation in the defect resistance, which widely varied with varying differential voltage between the defective plug surface and the backside wafer, as shown in Fig. 6. However, it is difficult to measure the charge-up voltage on each defective plug during electron irradiation. The open circles plotted in Fig. 6 represent the defect resistances at the charge-up voltage calculated by the circuit simulator considering the variation in the defect resistances of the defective plugs. This result shows that the charge-up voltage of the defective plug depends on the defect resistances. However, the difference between the simulated resistance and the measured resistance possibly becomes larger than 1.0% using a different SEM system. This difference mainly caused by the assumption of the energy distribution of the secondary electrons. This difference should be minimized by adjusting a parameter of the function L, which is determined from integrating the energy distribution of the secondary electrons when the electron energy is higher than $V_B$.

Fig. 8

Calibration curve obtained from the calculation considering measured I-V characteristics of defects formed on standard calibration wafers.

Figure 9 shows a calibration curve for ${\mathrm{SiO}}_2$ thickness at the bottom of the defect. It is noteworthy that the ${\mathrm{SiO}}_2$ thickness calibrated by these standard wafers is not exactly the same as the ${\mathrm{SiO}}_2$ thickness of the defective plug formed in the manufactured wafer, because the electrical conductivity of the residual ${\mathrm{SiO}}_2$ films at the bottom of the plugs slightly vary. However, the thickness of ${\mathrm{SiO}}_2$ is roughly estimated from the grayscale formed on the SEM image.

Fig. 9

Calibration curve for ${\mathrm{SiO}}_2$ thickness at bottom of defect.

4.1.

Experiments

Plug patterns on a wafer manufactured for an SRAM device were inspected using the developed in-line inspection method. At first, dark defects were detected by using an EB inspection system, i.e., a Hitachi High-Technologies I-5320. Next, the detected dark defects were reviewed by defect-review SEM, which, as explained above, was used to improve the equivalent-circuit model of the defective part.

To obtain the calibration curve for the SRAM pattern, the I-V characteristics of the normal plugs of the SRAM pattern were measured by a nano-prober. The measured resistances obtained from the I-V characteristics of the normal plugs were used to determine the resistance of the part of the equivalent circuit connected under the plug, shown in Fig. 2(b). As explained above, the resistance of the defective plugs on the standard calibration wafers was input to simulate the defective part of the equivalent circuit. After the calibration curve for the SRAM pattern was calculated from the improved equivalent circuit model, the resistances of the detected defects were estimated from the grayscale of the voltage contrast formed on the images of the SRAM pattern. Finally, the estimated defect resistances were compared with those measured by the nano-prober.

4.2.

Results and Discussion

The calibration curve obtained by considering the resistance of the intentional defects and that of the normal plug in the SRAM pattern is shown in Fig. 10. The normal plugs formed on the SRAM pattern are classified into four types. The first type was formed on a p-type diffusion layer; the second type was formed on an n-type one; the third type was connected to a gate electrode; and the fourth type was a shared contact plug connected to both a p-type diffusion layer and a gate electrode. The calibration curve of a plug connected to a p-type diffusion layer is almost the same as that of a shared contact plug. The measured voltage contrasts formed in the SEM images of the four types of normal plug patterns are plotted at the resistance of ${10}^8\mathrm{\Omega }$ in Fig. 10. The differences between the voltage-contrast calculations and measurements of the normal plugs are less than 8.0%. This calibration curve is applied below for estimating the resistances of defects formed on plug patterns in an SRAM device.

Fig. 10

Calibration curve for SRAM pattern.

Examples of SEM images of dark defects on a SRAM pattern are shown in Fig. 11. Two types of dark defects are observed on the images of the shared contact plugs. One is a dark defect with higher contrast, as shown in Fig. 11(a), and the other is a defect with lower contrast, as shown in Fig. 11(b).

Fig. 11

Examples of SEM images of a defect with higher contrast and a defect with lower contrast on an SRAM wafer.

Variation in voltage contrast formed on a defective plug for shared contacts is shown in Fig. 12. The grayscales are an average of the grayscales of pixels in the area of the defective plug. An error of the grayscales depends on the variation in $I_p$. To correct this error, the voltage contrast was determined from the difference between the averaged grayscale of normal plugs and that of a defective plug. It was normalized by the difference between the averaged grayscale of normal plugs and that of the ${\mathrm{SiO}}_2$ area in each SEM image. As a result, the voltage contrasts of the defective plugs formed in shared contact patterns are classified as two levels, as shown in Fig. 12. The higher contrasts, which were calculated from the grayscales of the darker defects, are about 100%; the lower contrasts, which were calculated from the grayscales of the slightly dark defects, are from 38% to 60%. The resistances of the dark defects were estimated to be ${10}^{12}\mathrm{\Omega }$ or higher. The resistances of the other defect with lower contrast were estimated to be from $1.0\times {10}^{11}$ to $3.0\times {10}^{11}\mathrm{\Omega }$. Examples of the resistances measured with a nano-prober at the charge-up voltage are plotted in Fig. 10. The plotted measured resistances were those at the charge-up voltage, which was calculated by the circuit simulator considering the measured IV characteristics of the defect formed on SRAM pattern. The resistance of the darker defect was too high to measure by a nano-prober. The measured resistances of the slightly darker defects agree well with the calculated calibration curve within an accuracy of an order of magnitude. The measured resistance has an error caused by variation in the voltage contrast formed in a field of view image. This variation is mainly due to the beam scan. The standard deviation of the voltage contrast of the normal plug in a field of view image is 12.0%. If the standard deviation of the voltage contrast of the defective plug is equal to that of the normal plug, the accuracy of this method is within an order of magnitude. This method is expected to be more accurate to more precise inspection. However, this accuracy is good enough to classify the defects according to the resistance value. Defects for the destructive analysis are efficiently selected using this method.

Fig. 12

Variation in voltage contrast measured from defect images formed on a plug for shared contacts. Voltage contrast is separated into two levels.

Schematic cross-sections of defects analyzed by TEM are shown in Fig. 13. A normal shared contact is connected to both a gate electrode and the silicon substrate. However, the defective plugs with higher contrast, shown in Fig. 13(a), are neither connected to the gate electrode nor the silicon substrate. The defective plugs are completely disconnected because of particles such as dust or other residue. The defective plugs with lower contrast, shown in Fig. 13(b), are connected only to the gate electrode, that is, not to the silicon substrate. They are prevented from connecting to the silicon substrate by particles or un-etched residues. Accordingly, positive charges on the plugs might leak through the gate dielectric to the silicon substrate.

Fig. 13

Schematic cross-sections of a detected defect with higher contrast and a defect with lower contrast.