Methods for joint optimization of mask and design targets for improving lithographic process window

Shayak Banerjee; Kanak B. Agarwal; Michael Orshansky

doi:10.1117/1.JMM.12.2.023014

11 June 2013 Methods for joint optimization of mask and design targets for improving lithographic process window

Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky

Author Affiliations +

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 12, Issue 2, 023014 (June 2013). https://doi.org/10.1117/1.JMM.12.2.023014

Abstract

Low-k ₁ lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower-level metals used for local routing, where bi-directionality and tight pitches give rise to lithography unfriendly layout patterns. However, there exists inherent unutilized flexibility in design shapes, e.g., one can modify such wires without significantly affecting design behavior. We develop two different techniques to simultaneously modify mask and design shapes during optical proximity correction (OPC) to improve lithographic yield of low-level metal layers. The methods utilize image slope information, which is available during OPC image simulations at no extra cost, as a measure of lithographic process window. We first propose a method that identifies fragments with low normalized image log slope (NILS) and then use this NILS information to guide dynamic target modification between iterations of OPC. The method uses a pre-characterized lookup table to assign a different magnitude of local target correction to different NILS bins. Next we develop an optimization flow where we derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample 1× (M1) layouts show that the use of SMATO reduces the process manufacturability index (PMI) by 15.4% compared with OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared with process window optical proximity correction (PWOPC), we observe 4.6% improvement in PMI at large (2.6× ) improvement in runtime.

Citation Download Citation

Shayak Banerjee, Kanak B. Agarwal, and Michael Orshansky "Methods for joint optimization of mask and design targets for improving lithographic process window," Journal of Micro/Nanolithography, MEMS, and MOEMS 12(2), 023014 (11 June 2013). https://doi.org/10.1117/1.JMM.12.2.023014

Published: 11 June 2013

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

;

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE