Clean pattern matching for full chip verification

Satomi Nakamura; Tetsuaki Matsunawa; Chikaaki Kodama; Takanori Urakami; Nozomu Furuta; Shunsuke Kagaya; Shigeki Nojima; Shinji Miyamoto

doi:10.1117/12.916316

14 March 2012 Clean pattern matching for full chip verification

Satomi Nakamura, Tetsuaki Matsunawa, Chikaaki Kodama, Takanori Urakami, Nozomu Furuta, Shunsuke Kagaya, Shigeki Nojima, Shinji Miyamoto

Author Affiliations +

Proceedings Volume 8327, Design for Manufacturability through Design-Process Integration VI; 83270T (2012) https://doi.org/10.1117/12.916316
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

Layout verification is essential in the cutting-edge generation. Generally, it uses a lithography simulation (Lithography Compliance Check: LCC) and requires a lot of calculation time. In order to reduce LCC time, we propose a clean pattern matching method by means of a "clean pattern library". The proposed method searches for patterns without hotspots (clean patterns) which usually occupy the most of the chip area. The conventional hotspot pattern matching method has no guarantee that unmatched area is hotspot-free, so LCC is usually applied to the unmatched area. On the other hand, the proposed matching method searches for "clean" patterns so that most of the area need not to be verified. As a result, LCC time can be reduced. This paper shows the detailed flow of the proposed matching method. We present the experimental results of layout verification in our 40nm system LSI designs and the effectiveness of the proposed method is confirmed.

Citation Download Citation

Satomi Nakamura, Tetsuaki Matsunawa, Chikaaki Kodama, Takanori Urakami, Nozomu Furuta, Shunsuke Kagaya, Shigeki Nojima, and Shinji Miyamoto "Clean pattern matching for full chip verification", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270T (14 March 2012); https://doi.org/10.1117/12.916316

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