It is well known that VLSI circuits must be designed to sustain the variations in process, voltage, temperature, etc. As a result, standard cell libraries (collections of the basic circuit components) are usually designed with large margin (also known as “timing slack”). However, in circuit manufacturing, only part of the margin will be utilized. The knowledge of the rest of the margin (over-designed timing slack), armed with models that link between timing domain and shape domain, can help to reduce the complexity of mask patterns and manufacturing cost. This paper proposed a novel methodology to simplify mask patterns in optical proximity correction (OPC) by using extra margin in timing (over-designed timing slack). This methodology can be applied after a conventional OPC, and is compatible with the current application-specific integrated circuit (ASIC) design flow. This iterative method is applied to each occurrence of over-designed timing slack. The actual value of timing slack can be estimated from post-OPC simulation. A timing cost function is developed in this work to map timing slack in timing domain to mask patterns in shape domain. This enables us to adjust mask patterns selectively based on the outcome of the cost function. All related mask patterns with over-designed timing slack will be annotated and simplified using our proposed mask simplification algorithm, which is in fact to merge the nearby edge fragments on the mask patterns. Simulations are conducted on a standard cell library and a full chip design to validate this proposed approach. When compared to existing OPC methods without mask simplification in the literature, our approach achieved a 51% reduction in mask fragment count, and this directly leads to a large saving in lithography manufacturing cost. The result also shows that timing closure is ensured, though part of the timing slack has been sacrificed.
Strong correlation between de-protection induced thickness reduction and amplified chemical reaction in the
exposed area of the chemically amplified resist (CAR) during post-exposure bake (PEB) has been established.
The optical properties of the resist film due to the thickness reduction can be detected using a spectroscopic
ellipsometer. In this paper, a rotating polarizer spectroscopic ellipsometer is developed and a proposed control
scheme is presented for signature profiles matching. With the implementation of the control scheme, wafer-towafer
critical dimensions (CD) uniformity is improved by 5 times.
Resolution enhancement techniques (RET) such as optical proximity correction (OPC) has become an integral part of the
fabrication of integrated circuits to maintain the edge placement integrity of the original circuit design. Conventional
OPC schemes are usually shape driven and full chip based, resulting in unpredictability in electrical behavior and huge
computational effort. To overcome these drawbacks, a new OPC methodology which is electrically driven and based on
cell-wise optimization is proposed. Simulation results when compared to conventional OPC approaches in the literature
demonstrate better timing accuracy with reduced mask cost. Depending of the circuit test-set, an average run-time
improvement between 3 to 8 times is achieved for circuit size with 100 - 400 cells. Further improvements can be
obtained by adopting a hybrid approach by only optimizing the timing performance of critical paths. For the hybrid
approach, better timing accuracy can be achieved while incurring little penalty on mask cost.
Conventional geometrical EPE-based OPC approach often results in complicated mask and requires expensive
computational effort. To address the mask complexity issue, a device performance-based OPC (DPB-OPC) algorithm
which operates based on parametric current, rather than desired layout pattern as in conventional OPC, has been
proposed to achieve considerable mask data saving. However, the performance gain is currently limited by the
comparatively longer run-time. To improve run-time efficiency of the previous work, we present a library-based DPBOPC
methodology in the paper. In particular, cell-wise OPC concept is deployed to explore its merit of run-time saving.
To counteract the performance degradation shift that caused by different surrounding environment, a localized DPBOPC
refinement can be selectively performed. When compared to full chip OPC, substantial run-time reduction is
achieved in the benchmark design.
Current approaches to control critical dimensions (CD) uniformity during lithography is primarily based on run-to-
run (R2R) methods where the CD is measured at the end of the process and correction is done on the next
wafer (or batch of wafers) by adjusting the parameter set-points. In this work, we proposed a method to monitor the various photoresist parameters (e.g. photoresist thickness, photoactive compound) and CD in-situ and in real-time. Through modeling and real-time identification, we develop new in-situ measurement techniques for the various parameters of interest in the lithography sequence using existing available data in the manufacturing process.
KEYWORDS: Semiconducting wafers, Photoresist materials, Mass attenuation coefficient, Lithography, Spectroscopy, Reflectivity, Microelectronics, Process control, Signal attenuation, Control systems
The rapid transition to smaller microelectronic feature sizes involves the introduction of new lithography technologies,
new photoresist materials, and tighter processes specifications. This transition has become increasingly
difficult and costly. The application of advanced computational and control methodologies have seen increasing
utilization in recent years to improve yields, throughput, and, in some cases, to enable the actual process to
print smaller devices. In this work, we demonstrate recent advances in real-time monitoring and control of these
photoresist parameters with the use of innovative technologies, control and signal processing techniques; and
integrated metrology to improve the performance of the various photoresist processing steps in the lithography
sequence.
Critical dimension (CD) or linewidth is one the most critical variable in the lithography process with the most
direct impact on the device speed and performance of integrated circuits. Photoresist thickness is one of the
photoresist properties that can have an impact on the CD uniformity. Due to thin film interference, CD varies
with photoresist thickness. In this paper, we present an innovative approach to control photoresist thickness in
real-time during thermal processing steps in the lithography sequence to control CD. As opposed to run-to-run
control where information from the previous wafer or batch is used for control of the current wafer or batch, the
approach here is real-time and make use of the current wafer information for control of the current wafer CD.
The experiments demonstrated that such an approach can reduce CD
non-uniformity from wafer-to-wafer and within-wafer.
KEYWORDS: Semiconducting wafers, Control systems, Lithography, Systems modeling, Convection, Thermal modeling, Temperature sensors, Data modeling, Sensors, Temperature metrology
We proposed an in-situ method to control the wafer spatial temperature uniformity during thermal cycling of
silicon substrate in the lithography sequence. These thermal steps are usually conducted by the placement of
the substrate on the heating plate for a given period of time. We have previously proposed an approach for
controling the steady-state wafer temperature uniformity in steady-state. In this paper, we extend the approach
by considering the dynamic properties of the system. A detailed physical model of the thermal system is first
developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and
fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time.
This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates
are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to
process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve
uniform wafer temperature is not possible in current baking systems. Any correction is done based on run-to-run
control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can
correct for any variations in the desired wafer temperature performance during both transient and steady state.
Experimental results demonstrate the feasibility of the approach.
During the Design-to-Manufacturing tape out flow, Optical Proximity Correction (OPC) is commonly adopted to correct
the systematic proximity-effects-caused patterning distortions in order to minimize the across-gate and across-chip
linewidth variation. With the continued scaling of gate length, the OPC correction scheme inevitably becomes more
aggressive nowadays; increasing the mask complexity and cost proportionally. This could partly be attributed to the
purely geometry-based OPC algorithm which tries to match every edge in the layout, without considering its actual
impact on circuit performance. Therefore, possibility exists for over-corrected OPC mask that bring slight improvement
in circuit performance at the expense of disproportionate higher cost. To simplify the mask design, we present a device
performance-based OPC (DPB-OPC) algorithm to generate the mask based on the performance matching criteria rather
than the geometrical pattern matching criteria. Drive current (Ion) and leakage current (Ioff) of transistor are chosen to
be the performance indexes in this DPB-OPC flow. When compared to the conventional OPC approaches, our proposed
approach results in simpler mask that achieves closer circuit performance.
Critical dimension (CD) is one the most critical variable in the lithography process with the most direct impact
on the device speed and performance of integrated circuit. The development rate can have an impact on the CD
uniformity from wafer-to-wafer and within-wafer. Conventional approaches to controlling this process include
monitoring the end-point of the develop process and adjusting the development time or concentration from
wafer-to-wafer or run-to-run. This paper presents an innovative approach to control the development rate in
real-time by monitoring the photoresist thickness. Our approach uses an array of spectrometers positioned
above a programmable bakeplate to monitor the resist thickness. The develop process and post-development
bake process is integrated into one equipment. The resist thickness can be extracted from the spectrometers
data using standard optimization algorithms. With these in-situ measurements, the temperature profile of the
bakeplate is controlled in real-time by manipulating the heater power distribution using a control algorithm. We
have experimentally obtained a repeatable improvement in controlling the end-point of the develop process from
wafer-to-wafer and within wafer.
Photoresist film thickness and extinction coefficient are two important properties which has an impact on critical
dimension (CD). Current approaches for estimating these resist film properties are based on the assumption of
a flat wafer. However, wafer warpage is common in microelectronics processing. In this paper, the effect of
wafer warpage on the accuracy of resist properties estimation is investigated and an in-situ calibration method
is proposed. Based on the proposed approach, we demonstrate how wafer warpage can be detected in real-time
using conventional reflectometers during the thermal processing steps in lithography.
A thermal processing module, which consists of a dense distribution of multivariate controlled heat/chill elements,
is developed to achieve temperature uniformity of a silicon wafer throughout the processing temperature
cycle of ramp, hold and quench in microlithography. In the proposed unit, the bake and chill steps are conducted
sequentially within the same module without any substrate movement. The unit includes two heating
sources. The first is a mica heater which serves as the dominant means for heat transfer. The second is a set
of thermoelectric devices (TEDs) which are used to provide a distributed amount of heat to the substrate for
uniformity and transient temperature control. The TEDs also provide active cooling for chilling the substrate
to a temperature suitable for subsequent processing steps. The feasibility of a practical system is demonstrated
via detailed modeling and simulations based on first principle heat transfer analysis.
Good alignment is needed in various wafer processes. Reflectometry is a well-established technique that continues to be widely used to monitor the thickness of wafer thin films. The use of a reflectometer was investigated to detect incorrect tilt and height of wafer placement. We found that it could be used in the spectroscopic or the monochromatic mode and provided results whether the wafer was bare or coated. We also found that the technique was somewhat more sensitive to tilt of bare wafers, and more sensitive to height displacements of coated wafers.
The design of an integrated bake/chill module for photoresist processing in microlithography is presented, with emphasis on the spatial and temporal temperature uniformity of the substrate. The system consists of multiple radiant heating zones for heating the substrate, coupled with an array of thermoelectric devices (TEDs) which provide real-time dynamic and spatial control of the substrate temperature. The TEDs also provide active cooling for chilling the substrate to a temperature suitable for subsequent processing steps. The use of lamp for radiative heating also provide fast ramp-up and ramp-down rates during thermal cycling operations. The feasibility of the proposed approach is demonstrate via simulations based on first principle heat transfer modeling. The distributed nature of the design also means that a simple decentralized control scheme can be used to achieve tight spatial and temporal temperature uniformity specifications.
An in-situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography is presented. Based on first principle thermal modeling of the thermal system, the temperature of the wafer can be estimated and controlled in real-time by monitoring the bake-plate temperature profile. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However as processes are subjected to process drifts, disturbances and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady-state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach.
Critical dimension (CD) or linewidth is one the most critical variable in the lithography process with the most direct impact on the device speed and performance of integrated circuit. The resist development step is one of the critical step in the lithography process that can have an impact on the CD uniformity. The development rate can have an impact on the CD uniformity from wafer-to-wafer and within-wafer. Non-uniformity in the time to reach endpoint is the result of non-uniformity in film thickness, exposure dosage and resist chemical compound. This can in turn lead to non-uniformity in the linewidth. Conventional approach to control this process include monitoring the end-point of the develop process and adjust the development time or concentration from wafer-to-wafer or run-to-run. This paper presents an innovative approach to control the photoresist development rate in real-time by monitoring the photoresist thickness. Our approach uses a spectrometer positioned above a bakeplate to monitor the development rate. The absorption coefficient can be extracted from the spectrometers data using standard optimization algorithms. With these in-situ measurements, the temperature profile of the bakeplate is controlled in real time by manipulating the heater power distribution using conventional proportional-integral (PI) control algorithm. We have experimentally obtained a repeatable improvement in the time to reach end-point for the develop process from wafer-to-wafer. Nonuniformity of less than 5% in the time to reach endpoint has been achieved.
Critical dimension (CD) or linewidth is one the most critical variable in the lithography process with the most direct impact on the device speed and performance of integrated circuit. The absorption coefficient is one of the photoresist properties that can have an impact on the CD uniformity. The absorption coefficient determined the required exposure dose for printing the features. Hence, nonuniformity in absorption coefficient across the substrate will lead to nonuniformity in the linewidth. This paper presents an innovative approach to controlling the within wafer photoresist absorption coefficient uniformity. Previous works in the literature can only control the average uniformity of the absorption coefficient. Our approach uses an array of spectrometers positioned above a multizone bakeplate to monitor the absorption coefficient. The absorption coefficient can be extracted from the spectrometers data using standard optimization algorithms. With these in-situ measurements, the temperature profile of the bakeplate is controlled in real time by manipulating the heater power distribution using conventional proportional-integral (PI) control algorithm. We have experimentally obtained a repeatable improvement in the absorption coefficient uniformity from wafer-to-wafer and within wafer. A 50% improvement in absorption coefficient uniformity is achieved.
This paper presents a novel wafer baking system that uses hot air streams as heating media and achieves good temperature uniformity across the entire wafer surfaces during the baking process. Wind tunnel experiments have been carried out to verify the concept of using hot air streams for wafer baking. A simple prototyping wafer baking system has been designed and fabricated, and experiments of the baking process have been conducted. Good temperature uniformity across the wafer surface has been achieved. The experimental results match well with the computer fluid dynamics (CFD) simulation results. It is observed that the velocity of the airflow has significant influence on the temperature transient responses. Further optimization of the parameters of the baking system and analytical modelling studies are currently under way.
Thermal processing of photoresist are critical steps in the microlithography sequence. The post-expose bake steps for current DUV chemically-amplified resists is especially sensitive to temperature variations. Requirements call for temperature to be controlled to within 0.1 degree(s)C at temperature between 70 degree(s)C and 150 degree(s)C. The problem is complicated with increasing wafer size and decreasing feature size. Conventional thermal system, which utilizes single or dual zone heating, is no longer able to meet these stringent requirements. The reason is that the large thermal mass of conventional hot plates prevents rapid movements in substrate temperature to compensate for real-time errors during transients. The implementation of advanced control systems with conventional technology cannot overcome the inherent operating limitation. A spatially-programmable thermal processing module for the baking of 300 mm wafers has been developed.
An optimal control scheme is designed to improve repeatability by minimizing the loading effects induced by the common processing condition of placement of a semiconductor substrate at ambient temperature on a large thermal-mass bake plate at processing temperature. A model-based optimal controller is presented based on minimum time control strategy for minimizing the worst-case deviation from a nominal temperature set-point during the load disturbance condition. This results in a predictive controller that performs a pre- determined heating sequence prior to the arrival of the substrate as part of the resulting feedforward/feedback strategy to eliminate the load disturbance. The controller is easy to design and implement for conventional thermal processing equipment. The minimum time control formulation also makes it more suitable for on-line implementation such as automatic on-line tuning of feedforward controller. Experimental results are performed for a commercial conventional bake plate and depict an order-of-magnitude improvement in the settling time and the integral-square temperature error between the optimal predictive controller and a feedback controller for a typical load disturbance.
KEYWORDS: Semiconducting wafers, Temperature metrology, Data modeling, Control systems, Computer programming, Feedback control, Photomasks, Photoresist processing, Temperature sensors, Thermal modeling
An optimal control scheme is designed to improve repeatability by minimizing the loading effects induced by the common processing condition of placement of a semiconductor wafer/photomask at ambient temperature on a large thermal-mass bake plate at processing temperature. The optimal control strategy is a model-based method using linear programming to minimize the worst-case deviation from a nominal temperature set-point during the load disturbance condition. This results in a predictive controller that performs a pre-determined heating sequence prior to the arrival of the wafer as part of the resulting feedforward/feedback strategy to eliminate the load disturbance. This procedure is based on an empirical model generated from data obtained during closed-loop operation. It is easy to design and implement for conventional thermal processing equipment. Experimental results are performed for a commercial conventional bake plate and depict an order-of-magnitude improvement in the settling time and the integral-square temperature error between the optimal predictive controller and a feedback controller for a typical load disturbance.
KEYWORDS: Temperature metrology, Semiconducting wafers, Photomasks, Photoresist materials, Chemical elements, Photoresist processing, Control systems, Feedback control, Process control, Silicon
Preliminary performance data is presented for a new thermal processing module. The system is directed towards conducting the temperature sensitive baking and chilling steps for chemically amplified photoresists. The module is comprised of 49 individual heating zones. The zones can be controlled independently with separate temperature sensing, actuation and feedback control mechanisms. A supervisory control strategy is applied to coordinate the individual zones. An in-situ chill plate is used to enable a temperature controlled cool-down phase without the need for substrate movement. Results are presented to demonstrate temperature control over the plate to within plus or minus 0.02 degrees Celsius. Wafer temperature is controlled to within plus or minus 0.05 degrees Celsius as measured at 5 sites. Photomask processing results are presented depicting steady-state control to within plus or minus 0.05 degrees Celsius as measured at 16 sites within one quadrant of the substrate. The advantages of the system are discussed including better temperature uniformity than conventional systems and the ability to conduct multiple experiments in a single run by biasing the setpoint across the substrate.
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