Overlay control continues to be a critical aspect of successful semiconductor lithography processing, with overlay control systems becoming more and more elaborate to meet the requirements of advanced semiconductor nodes. Sampling optimization is especially important including the number of overlay measurements to perform on each wafer, the number of wafers to measure per lot, and where exactly to measure on each wafer. Conventional sampling optimization methodology is to collect dense data for a short period and use this data to optimize the locations to measure on the wafer. In recent years, rule-based sampling was introduced to relax this data requirement and improve the time to result. However, in both scenarios, one single sample plan is generated in offline optimization, which is then used in high volume manufacturing (HVM) without change, hence named “static sampling”. In this paper, we introduce a “dynamic sampling” approach, where multiple rule-based sample plans are generated, that complement each other by measuring different locations on the wafer, while meeting spatial and population balancing criteria. These sample plans can then be used in an alternating manner on a per-wafer basis (wafer-by-wafer dynamic sampling) and per-lot basis (lot-by-lot dynamic sampling) in HVM. In this paper, we first demonstrate the risks and the inherent trade-offs associated with static sampling by using overlay budget breakdown and best/worst case advanced process control (APC) simulations. We then characterize the overlay control improvement potential of dynamic sampling schemes through APC simulations using multiple metrics: on-product overlay, rework overlay and monitoring accuracy. Finally, we calculate the on-product overlay versus throughput cost function analysis and determine which dynamic sampling scheme is the most useful for which throughput conditions.
In advanced technology nodes, the focus window becomes tighter to achieve smaller CD features while maintaining or improving product yields. During the past decades, focus spot monitoring (FSM) has been a critical topic in high-volume manufacturing, not only for minimizing the contamination impact on focus performance but also for scanner productivity concerns if wafer table cleaning needs to be executed. Although there is a dedicated FSM option combined with automatic wafer table cleaning from the exposure tools, the users often need to be careful to design the threshold and monitor the area by different products and layers, to prevent false positive alarmsthat impact the productivity of scanners. In some cases, a small focus spot threshold can cause more false positive alarms at the wafer edge area due to the edge roll-off effect on the wafer table and steep wafer topography, which brings difficulty to detecting small focus spots due to contamination. In our study, we compare the classic FSM provided by exposure tools to a newly developed automated FSM mechanism. There are several mathematical steps and approaches implemented into our new type of FSM to reduce false positive focus spot alarms. For comparison, we evaluated the performance of classic and new FSM methods on different layers, which showed special topography, edge roll-off effect, or strong intra-field signature. Finally, a new robust and user-friendly FSM method has been demonstrated and proven that even with a tight threshold, the false positive alarm especially around the wafer edge area can be fully eliminated.
In a leading-edge high-volume manufacturing fab, lithographers focus on searching for a suitable alignment layout strategy to cover process-induced overlay variation. However, how to minimize scanner cross-chuck overlay impact also draws attention due to WPH loss from chuck dedication. In this paper we evaluate a novel algorithm to analyze lithography scanner process/metrology data and introduce a new KPI called “model accuracy” for alignment sampling layout strategy creation, which takes into account robustness index as wafer-to-wafer/chuck-to-chuck variation. Combined with simulated overlay performance, an optimal alignment layout strategy is recommended for a maximum coverage of cross-chuck overlay, which leads to maximum productivity.
In recent years, advances in semiconductor technologies have resulted in the continuous shrinkage of the process window required to fabricate a device, and specifically, the shrinkage of the overall overlay budget of the critical layers. Among other variables, a key contributor of wafer-to-wafer overlay variations is scanner alignment strategy. In high-volume manufacturing (HVM), the reduction in alignment mark count can lead to productivity improvement, however, that tradeoff impacts the scanner alignment layout and overlay model performance. In this paper, we present a comprehensive investigation of an in-line production experiment and simulation results to evaluate overlay performance by cooptimization of scanner alignment mark count, layout for High Order Wafer Alignment (HOWA) model.
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