This paper characterizes, studies and breaks down different components of OL inaccuracy and NZO for a back-end-of-line (BEOL) metal layer on an advanced node testsite. In this study, NZO is characterized by measuring SEM OL and OM OL at the same locations across the wafer and at various process steps.
To understand the root-cause of the NZO, process-induced OL shift on both SEM OL and OM OL from ADI, to AEI and finally to CMP are characterized and discussed. It shows that process-induced OL shift is a major contributor to OL inaccuracy and NZO and is affected by the CD and pitch of the measured feature. This paper also studies OL difference between kerf (where OM OL marks are typically located) and in-die (where actual device are located) overlay. Lastly, OL delta between the two OL measurement techniques was studied by measuring the same OL mark with both SEM OL and OM OL tools.
This paper concludes with a breakdown of key contributors to OL inaccuracy and NZO. It provides recommendations and future work on utilizing SEM OL in conjunction with OM OL to address the challenging overlay inaccuracy and NZO requirement for advanced logic node.
Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.
Predicting the best preforming overlay marks for a set of layers in a new technology process flow would provide a powerful tool, which could potentially streamline the time consuming measurement process search for the optimal overlay mark. This is challenging because integration of the next generation of transistors and interconnects is becoming increasingly complex, so evaluating overlay mark performance in isolation yields partially valuable results. We show how process emulation can be used to evaluate overlay marks in conjunction with optical simulations for the critical patterning levels, and only the marks that perform well in simulation are allowed on the final mask, thereby predicting the best overlay marks for a particular technology. To make this methodology useful, it is important to cater each analysis to the specific materials being used, their optical properties, and the integration scheme of the technology. This is done as follows: (a) the optical properties of the materials being used are extracted using standard metrology tools, (b) the process flow of an existing technology is emulated, (c) an initial optical model is created with the inputs for settings like wavelength and focus form the metrology tool configuration, (d) the images from the overlay tool for the existing technology are analyzed to calibrate for unknowns such as numerical aperture and coherence, and finally, (e) the calibrated model is used on future technology flows to evaluate the performance of overlay marks. We will illustrate the validity of this methodology using specific examples and highlight its predictive capability.
This paper presents a new overlay metrology target design and scheme referred as MoiréOVLTM. It utilizes Moiré patterns of two overlapping gratings to amplify the kernel response to overlay misalignment and thereby has the potential to enhance kernel sensitivity, detectability and measurement accuracy. A Self-referenced (SR) MoiréOVL design scheme, which enables MoiréOVL to be measured with existing image-based overlay tools is proposed and evaluated on a contact layer. This paper demonstrated the feasibility of SR-MoiréOVL on existing IBO tools. When comparing to the reference SEM-based overlay, a magnification factor of 6.9X with an R2 of 0.96 and a calibrated intercept of 0.34nm was observed on wafer. Comparison between MoiréOVL and POR IBO on TIS, residuals, precision and TMU is presented. Lastly we present the idea of a Self-calibrated (SC) MoiréOVL scheme to calibrate the magnification factor on the fly during measurement for enhanced usability.
Shrinking on-product overlay (OPO) budgets in advanced technology nodes require more accurate overlay measurement and better measurement robustness to process variability. Pupil-based accuracy flags have been introduced to the scatterometry-based overlay (SCOL) system to evaluate the performance of a SCOL measurement setup. Wavelength Homing is a new robustness feature enabled by the continuous tunability of advanced SCOL systems using a supercontinuum laser light source in combination with a flexible bandpass filter. Inline process monitoring using accuracy flags allows for detection, quantification and correction of shifts in the optimal measurement wavelength. This work demonstrates the benefit of Wavelength Homing in overcoming overlay inaccuracy caused by process changes and restoring the OPO and residual levels in the original recipe.
As semiconductor technology nodes keep shrinking, ever-tightening on-product overlay (OPO) budgets coupled with continuous process development and improvement make it critical to have a robust and accurate metrology setup. Process monitoring and control is becoming increasingly important to achieve high yield production. In recently introduced advanced overlay (OVL) systems, a supercontinuum laser source is applied to facilitate the collection of overlay spectra to increase measurement stability. In this paper, an analysis methodology has been proposed to couple the measured overlay spectra with overlay simulation to extract exact process information from overlay spectra. This paper demonstrates the ability to use overlay spectra to capture and quantify process variation, which in turn can be used to calibrate the simulation stacks used to create the SCOL (scatterometry-based overlay) and AIM overlay metrology targets, and can be fed into the fab for process monitoring and improvement.
Prime silicon wafers are ideal substrates for lithographic patterning, with tight flatness specifications for focus control. Process engineers are painfully aware that in-process product wafers can substantially depart from this ideal substrate. Wafer processing can induce non-flatness leading to focus problems, or distort the wafer leading to overlay issues. Thus processes from outside the lithography sector can impact yield by ruining lithographic pattern quality. Double-sided optical interferometric metrology is the standard method to assess the flatness of blank silicon wafers. In the last several years, a similar Patterned Wafer Geometry (PWG) metrology tool is able to measure in-process patterned wafers. The apparent surface seen by an interferometer may be different than the true surface due to transparent thin films, a discrepancy that we call "false topography". Modeling results will demonstrate the use of a thin opaque film to reduce the problem. PWG metrology offers compelling advantages for the practical investigation of process-induced focus and overlay problems. The paper will include several examples of process learning from PWG metrology.
Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.
Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.
This paper describes the joint development and optimization of an advanced critical dimension (CD) control methodology at IBM’s 300 mm semiconductor facility. The work is initially based on 22 nm critical level gate CD control, but the methodology is designed to support both the lithography equipment (1.35 NA scanners) and processes for 22, 20, 18, and 14 nm node applications. Specifically, this paper describes the CD uniformity of processes with and without enhanced CD control applied. The control methodology is differentiated from prior approaches1 by combining independent process tool compensations into an overall CD dose correction signature to be applied by the exposure tool. In addition, initial investigations of product specific focus characterization and correction are also described.
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