A 3D direct detection imaging laser radar was developed and tested to demonstrate the ability to image objects highly obscured by foliage or camouflage netting. The LADAR provides high-resolution imagery from a narrow pulse-width transmitter, high frequency receiver, and 3D visualization software for near-real-time data display. This work accomplished under DARPA contract number DAAD17-01-D0006/0002.
A commercial version of the 3D Artificial Neural Network has been developed under a collaborative effort between JPL and Irvine Sensors, sponsored by BMDO and the U.S. Air Force. It is capable of continuous trillion eight bit multiply and add operations per second while consuming under ten watts. Its architecture, input-output characteristics, and performance data will be presented.
ISC has developed an unique form of bump bonding based on a plug and socket concept which allows high density reflow solder array interconnects. Solder bumps with diameters of 50 microns and heights of 15 microns are plugged into sockets of photo definable polyimide 75 microns in diameter and 10 microns high. The technique is used to flip chip bond infrared detector arrays to Z-technology modules without the need for complex aligner-bonder tooling. The same method has been used for die interconnection bonding to substrates and motherboards, module to module interconnect array bonding and die to module bonding. The inherent self-alignment which occurs during reflow of an array of solder bumps has been shown useful in obtaining precise, 1 micron range, alignment accuracy between electro-optical components, such as gallium arsenide light emitting diodes and polymer waveguides deposited on a silicon substrate. The same plug and socket technology is being extended for applications using compliant polymer bumps.
Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.
Visible and infrared focal planes are becoming ever larger and more complicated, but the real estate for unit cell electronics is diminishing. Applications such as High Definition Television require very large format focal plane arrays and complex post image processing prior to data transmission. The authors describe in this paper a technique of combining an active pixel CMOS sensor, or a CCD image capture device with analog to digital conversion and data compression circuitry on the focal plane in a unique Z-technology architecture. This architecture incorporates a stack of signal processing integrated circuits physically connected below the image capture device which provides up to 10 times the unit cell electronics real estate for the data conditioning. This paper focuses on the interconnect techniques between the image capture device and the post processing electronics.
ISC has completed test on an IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (A/D) converters with non-uniformity correction per channel and a digital multiplexer. The single slope class of A/D conversion is described, as are the unique variations required for incorporation of this technique for use with on-focal plane detector readout electronics. This paper describes the architecture used to implement the digital on-focal plane signal processing functions. Results from measured data on a test IC are presented for a circuit containing these functions operating at a sensor frame rate of 1000 hertz.
Z-Plane memory packaging technology utilizes the process of stacking integrated circuits (ICs) to each other in order to increase packaging density. This paper will discuss how Z-plane technology can be applied to memory systems used in high frame-rate imaging systems. 1.
This paper provides an overview of the current state-of-the-art HYMOSS (Hybrid Mosaic On Stacked Silicon) Z-technology. In the first part of this paper, an introduction to the HYMOSS physical characteristics is presented. This includes a description of the stacked substrates (cube) and mounting hardware (module). The basic steps in manufacturing HYMOSS are covered. The paper concludes with a description of the two newest endeavors for HYMOSS technology: stacking of superconducting ICs, digital memory, and processor ICs.
Design approaches to tactical air defense are outlined. A SAM and an air-to-air missile trajectory are used to optimize a system design for maximum target detection range, taking system noise and background clutter noise into account. Detection ranges of 30 km are found to be feasible except for bearing angles close to 90 and 270 deg when the background is between 35 and 75 km distant. Methods to operate in these gaps are suggested. For a 2D Dynamic Stare simulation using a real earth background, background noise was cut by five orders of magnitude, representing a base case type of performance for Dynamic Stare. Changes to make the system high resolution and high sensitivity are discussed.
The fabrication of the first Z-technology module with 128 active layers of readout electronic circuitry is being pursued. Several issues which will be investigated regarding the 128-layer module build, such as photolithographic processing at the edge of the module (edge effects) and module buttability, are discussed in this paper. Other topics which are covered apply to future applications of fully populated HYMOSS modules. These topics include possible reductions of thermal mass for quick cool-down time applications and improvements of end-to-end yield for low-cost applications.
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