If the minimum die area is the main objective of an ASIC application, then each critical layer will have bi-directional
mask layout. Then advanced litho technology is required to print the layers with single exposure lithography. If however
yield, electrical robustness and variability have higher priority than minimum die area, than unidirectional patterning can
be a good alternative. However, then the bi-directional layout of, especially the active area- and gate-layer, must be
redesigned in an unidirectional layout (at the expense of a larger cell-area). Moreover, if a design split in two orthogonal
unidirectional layouts can be made then the so-called cut-mask technology can be used: this is a (well-known) double
patterning technology. This paper discusses three different cut-mask compatible redesigns of the gate-layer of a complex
flip-flop cell, to be used in robust, low-cost low-power CMOS-logic applications with 45 nm ground rules and 180 nm
device pitches. The analogue circuit simulator from Cadence has been used. The results obtained with ASML's
lithography simulator, "Litho Cruiser", show that cut-mask patterning gives superior CD- and end-of-line control and
enables Design Rules with less Gate-Overlap. This again gives the circuit-designer more design freedom for choosing
the transistor width. Furthermore, the cut-mask compatible layouts can even be processed with high-NA dry KrFlithography
instead of advanced single exposure ArFi lithography. The designs are compared with a reference design
which is a traditional minimum area design with bi-directional layout.
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