As 193-nm immersion lithography will likely be required to be extended beyond 40-nm half-pitch, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for double patterning with extendibility to sub-10-nm half-pitch division, which is a very promising candidate for advanced logic nodes. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase-shift mask features, which impart phase shifts other than 180 deg or 0 deg. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure using a modified attenuated phase-shift photomask, followed by a low-contrast development process around the sensitivity limit, is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch while including some predetermined line cut locations.
Publisher’s Note: This paper, originally published on 4/12/2013, was replaced with a corrected/revised version on
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As 193 nm immersion lithography may be required to be extended beyond 20 nm node, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for 22 nm half-pitch double patterning, with extendibility to sub-10 nm half-pitch pitch division. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase shift mask (attPSM) features which impart phase shifts other than 180 or 0 degrees. Such features can be accommodated in the process flow for fabricating phase shift masks by the definition of one or two extra layers of processing in the mask shop. Aerial image simulations show this photomask design is more effective in generating sloped foot profiles in the photoresist than simply using sub-resolution features or reducing the width of the clear region. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure of a low-contrast photoresist around the sensitivity limit using a modified attenuated phase-shift photomask is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch with irregularly arranged breaks, or 'cuts' in the lines.
New non-volatile memory, like RRAM, needs high aspect ratio (AR) bi-layer resist (BLR) pillar pattern to act as etch mask for sub-50 nm cell metal pillar definition [1]. HSQ/AR3 resist pillar is still not enough for patterning RRAM pillar since (1) AR is limited at ~7 which is still marginal in etching resistance, (2) BLR resist pillar CD is limited by dry development positive CD-bias, (3) BLR resist pillar is easy to collapse during venting to air, and (4) BLR resist pillar AR is lower for looser pillar densities which degrades the etching resistance. Tone reverse process flow for forming RRAM pillar is developed in this study to overcome these drawbacks. Thermal reflow assists the formation of sub-30 nm contact holes (C/Hs) on ZEP520A e-beam resist. Experimental results are summarized below. All the resolved CDs of C/H on ZEP520A with designed CD (DCD) of 40-100 nm are larger than 100 nm without proximity effect correction (PEC) on blank RRAM film stacking substrate. Smallest etched C/H on LTO after thermal reflow process is 14.4 nm. CD-bias of etched C/H on LTO relative to that of resist C/H after thermal reflow is larger for looser C/Hs. Thermal reflow of ZEP520A is C/H size before reflow, density, sidewall profile and reflow time dependent. NiOx hard mask is apparently without deposited into C/H smaller than 20 nm due to PVD deposition limit since the NiOx dot image disappeared after etching of LTO film for tone reverse. Smallest CD of TiN/Ti/HfOx RRAM pillar by tone reverse process flow is 28.8 nm using NiOx hard mask dot CD of 22.9 nm formed on 20.5 nm etched C/H on LTO after reflow. Uniform CD distribution of designed C/Hs result in uniformly distributed CDs after reflow / LTO etching / RRAM pillar formation. In summary, tone reverse process flow for RRAM pillar formation is successfully developed which has potential for patterning RRAM pillar of CD smaller than 20 nm in the help of NiOx hard mask deposition by atomic layer deposition (ALD) into oxide C/H in the future.
New applications on memory and logic devices need to form line shape pattern below 20 nm. Most of the prior articles for studying HSQ line CD resolution applied hot or cold (non-room temperature (RT)) development, salty development, KOH-based development or high concentration TMAH developer (like 25%) to push CD resolution to below 10 nm but these methods are not standard IC process compatible with 2.38% TMAH development at RT. E-beam lithography processes are applied to investigate CD resolution on RRAM film stacking of TiN/Ti/HfOx with or without proximity effect correction (PEC). Both dose and shape (line CD and pitch) modulations are applied in this study to obtain finest line width resolution using IC process compatible 2.38% TMAH developer at RT. Experimental results are summarized below. Lowest base dose of HSQ for pattern to be resolvable is larger than 1,000 (μC/cm2). Smallest line CD of 13.1 nm for designed CD of 5 nm (G4) is resolved to 2 separate lines on R1st dense-line pattern with e-beam dose of 5,000 (μC/cm2) assisted by dose PEC. Two lines of R1st dense-pattern is merged to single line of 14.7 nm at 10,000 (μC/cm2). 2lines dense-line pattern is clearly resolved to 2 separate lines at 1,500 (μC/cm2) but merged to one line at 2,000 (μC/cm2). Iso-line on the right of two dense-lines of 2lines pattern contributes backscattered dose which increases the line width. 5lines dense-line pattern could only resolve to 18.3 nm. Iso-line R1st_1L is resolvable to 18.5 nm with uniform distribution of CD across the line and 13.6 nm is also resolved with more rough line edge. In summary, sub-14 nm line width of HSQ could be resolved by the combination of e-beam dose and shape modulations using standard 2.38% TAMH developer. This process is suitable for applications using metal oxide films.
High AR bi-layer resist (BLR) pillar with organic underlayer (UL) is inevitable for etching of thick RRAM film
stacking considering etch selectivity to avoid collapse. Selection of UL is a key factor to determine the AR of
BLR pillar and selectivity during etching of hard mask (HM) and RRAM film stacking. In this work, e-beam
patterning of HSQ pillar under various e-beam dose conditions, pattern density and HSQ thicknesses are studied
on carbon highly contained UL TBLC-100PM. Hard mask layer of low temperature nitride (LTN) or oxide (LTO)
above TiN/Ti/HfOx RRAM film stacking are also studied for achieving highest HSQ CD resolution by reducing
e-beam proximity effect. Fogging effect is studied with various e-beam dose of the L/S=1/20 isolated pillar array
which is far from the other arrays of 36 μm.
Experimental results are summarized below. Etch rates (etch resistance) of TBLC-100PM UL under fluorine or
chlorine-based plasmas are lower (higher) than that of AR3-600 UL with low carbon contained. Thicker LTN
HM is necessary for higher HSQ pillar CD resolution. HSQ pillar CD resolution on LTO HM is higher than that
on LTN HM. Smallest CD of HSQ pillar is 23.1 nm. Fogging effect is strong for TBLC-100PM where e-beam
dose could affect the shape of HSQ pillar of neighboring array. This is not observed for AR3-600 UL. HSQ pillar
CD resolution is highest for HSQ coated at 2000 rpm. Small change of HSQ coating speed could degrade CD
resolution and imaging contrast drastically which may come from the fogging effect.
The optimized dry development condition of low-k etcher obtained before is transferred to and optimized in
DPSII metal etcher in this study to avoid resist pillar collapse, etch residual magnification, process continuity
and tool simplicity. Three key process parameters of oxygen flow rate, bottom power and e-chuck temperature
are studied for vertical pillars with various pattern densities. HSQ pillar patterning is transferred from diluted
Fox-12 to commercialized XR1541-002 where the film thickness and patterned CD are matched. LTN hard
mask (HM) of 100 nm thick above RRAM film stack is deposited for reducing proximity effect of
XR1541-002 and improving etch resistance.
Experimental results are summarized below. Highest AR of ~3.9 for HSQ/AR3 BLR semi-dense L/S=1/3
pillar with vertical profile is obtained with optimized dry develop condition of O2, N2, flow rates, chamber
pressure and temperature, top and bottom power of 8, 5, sccm, 3 mTorr, 80oC, 200 and 100 watts respectively.
AR is lower for looser pattern density. Oxygen flow rate and bottom power are the most critical process
parameters for obtaining high AR BLR pillar and most vertical profile of pillar, just like the case of low-k
etcher. E-chuck temperature is critical in profile control. Etch residual is magnified to broaden LTN pillar CD
and degrade CD uniformity (CDU) if its etch process is not immediately continued after dry development
process.
Multiple patterning is the only known way to extend current 193 nm immersion-based optical lithography beyond
40 nm half-pitch. A highly effective technique for multiple patterning uses self-aligned etched spacers to define the
tightest pitch lines as critical features. However, to complete the patterning, the lines must be cut with at least one
separate additional exposure. In order to reduce the costs associated with multiple cut locations, it is proposed to group
the locations into portions of larger features. Specifically, the cut locations can be the intersection of the spacer lines and
the overlap of at least two polygons of opposite exposure polarity. The cost reduction is determined by the reduced
number of exposures, as well as the looser pitch and dimensions of the exposures. Besides cost reduction, greater
immunity to exposure shot noise (if EUV or EBL is used for cutting) is provided by the use of larger polygons. The
benefits of complementary polarity patterning based on these key issues will be analyzed for the 10 nm half-pitch
application, and extensions to even smaller half-pitches will be discussed.
Extreme Ultraviolet Lithography (EUVL) reflective mask blank development includes low thermal expansion material fabrication, mask substrate finishing, reflective multi-layer (ML) and capping layer deposition, buffer (optional)/absorber stack deposition, EUV specific metrology, and ML defect inspection. In the past, we have obtained blanks deposited with various layer stacks from several vendors. Some of them are not commercial suppliers. As a result, the blank and patterned mask qualities are difficult to maintain and improve. In this paper we will present the evaluation results of the EUVL mask pattering processes with the complete EUVL mask blanks supplied by the commercial blank supplier. The EUVL mask blanks used in this study consist of either quartz or ULE substrates which is a type of low thermal expansion material (LTEM), 40 pairs of molybdenum/silicon (Mo/Si) ML layer, thin ruthenium (Ru) capping layer, tantalum boron nitride (TaBN) absorber, and chrome (Cr) backside coating. No buffer layer is used. Our study includes the EUVL mask blank characterization, patterned EUVL mask characterization, and the final patterned EUVL mask flatness evaluation.
The use of a reflective mask in extreme ultraviolet (EUV) lithography requires illumination of the mask at a small but obliquely incident angle. This results in an inherent asymmetry in the diffraction pattern from the mask. This asymmetry results in a shift of the image at the wafer. The image shift depends on the mask structure and the exposure condition. The thicknesses of the patterned mask layers, specifically, the absorber and anti-reflection layer (ARL), are particularly important for the image formation. A rigorous approach to simulating these effects is required. In this paper, a fast frequency-domain method for simulating EUV masks with the underlying multilayer is used for the study of various mask variation effects on image placement as well as linewidth, for nested 35 nm and 25 nm lines. Results indicate that EUV radiation reflected from the mask before entering the multilayer cannot be neglected. Consequently, it is of utmost importance to maintain better than ±1 nm control of absorber thickness and ARL thickness over the entire mask, in order to minimize the CD impact of variations in reflectance swing.
Optical lithography continues to be extended with shorter exposure wavelength and higher numerical aperture tools. Strong resolution enhancement techniques such as alternating aperture phase-shifting utilize 2-beam imaging to achieve effective spatial frequency doubling, high DOF, and ultralow k1. For these techniques, unpolarized light exposure latitude worsens significantly for tighter pitches and smaller linewidths. In addition, the mask error factor begins to become polarization-dependent. Due to vector interference effects, TE-polarized light (electric field polarized parallel to line) provides better imaging than TM-polarized light (electric field perpendicular to line). Suppression of TM-polarized light will therefore enable aggressive subwavelength imaging. In this paper, we apply rigorous electromagnetic simulations to evaluate the typical dimensions of photomask features in order for them to exhibit TM polarization suppression. Subwavelength absorbing features with high aspect ratio are one possible way of achieving adequate polarization selectivity on a photomask. TE polarization selectivity for darkfield binary and alternating aperture strong phase-shifting masks can also be achieved with the use of smaller spaces and/or thicker absorbers. Throughput is traded off against polarization selectivity since there is also significant absorption of TE-polarized light by the polarizing features. Polarization-selective imaging solutions based on thick Cr photomask blanks are presented.
As requirement of CD uniformity on photomask continue to tighten with advanced logic and memory devices, new process technologies will be needed to be developed to address the gap of process capability. For instance, a less than 20 nm CD range will be required on a 0.18 micrometer generation logic devices with a nominal field area of 120 X 120 mm. New technologies such as high energy e-beam write (to reduce forward scattering), advanced e-beam photoresist and plasma etch processes are currently being developed to achieve such stringent CD uniformity specifications. One of the key issues of plasma etch technology is related to microloading effects which accounts for a major portion of CD budgets. In this work, an engineering test mask was designed to identify etch microloading mechanisms and to improve performance of a standard Magnetic-Enhanced Reactive Ion Etch (MERIE) process. Additional comparison of CD microloading was also made with an Inductively-Coupled Plasma (ICP) etch process.
Fabrication of 0.18 micrometers generation clearfield logic device photomask with plasma etch was compared with wet etch method in current 0.25 micrometers mask technology. Spatial consistency between the resist develop and plasma etch modules was critical to achieve < 25 nm CD rng manufacturable process. CD linearity for 0.6 to 3.0 micrometers lines and isolated-nested CD bias for 1.0 micrometers lines were both improved with the plasma etch process. Resist loading and proximity effect is critical for plasma etched clearfield mask and can account for up to 20 nm range of overall CD budget.
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