Edge placement error (EPE) is a critical indicator for the imaging performance of semiconductor technology nodes, and is among others influenced by writing errors on the reticle. The impact of global mask variations is generally well understood and local variations are often considered to have a similar behavior. In this contribution we highlight the differences between the local and global mask variations and their impact on CD and placement in resist. We discuss the concept of local Mask Error Enhancement Factor (MEEF) and the impact of mask perturbation on neighboring structures within a certain interaction length. We show that local mask variations have a significantly smaller effect than global effects, which can have an influence on mask requirements. We show results of HyperLith simulations for a DUV use case of staggered contact holes arrays. We explore the prediction of the impact in resist of random mask fingerprints using impulse responses from single contact hole perturbation. We show that such prediction can be used to calculate the global MEEF from the local effects. The simulation results are compared to experimental data, measured in resist with CDSEM.
With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.
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