The on-product overlay roadmap demands an aggressive overlay requirement in the advanced node. Currently the on-product overlay is dominated by effects coming from wafer processing and overlay target detectability. Processing effects such as symmetric stack variation and asymmetric overlay target deformations are expected to become limiting for accurate overlay measurements in future nodes
. Increased accuracy requirements and overall complexity in product stacks require a sensor with a higher flexibility. To address this an advanced metrology system is introduced in the fab, providing full flexibility in the selection of measurement wavelengths. On top of the wavelength flexibility, the increased wavelength switching speed enables the use of asymmetry robust recipes by combining multiple wavelength measurements at each overlay target.
In this paper we will introduce a method to select the most accurate multi-wavelength recipe that provides significant improvement in accuracy compared to the best single wavelength recipe. We will introduce KPIs to monitor the health of the multi-wavelength measurement. The KPIs are reported per site indicating the accuracy for every measured point.
Additionally we will show our steps towards the recovery of the points flagged by multi-wavelength KPI by a combination of measuring more wavelengths and an accuracy guided region of interest selection.
KEYWORDS: Overlay metrology, Semiconducting wafers, Etching, Polarization, Metrology, Scanning electron microscopy, Physics, Signal processing, Monte Carlo methods, Semiconductor manufacturing
Success of diffraction-based overlay (DBO) technique1,4,5 in the industry is not just for its good precision and low toolinduced shift, but also for the measurement accuracy2 and robustness that DBO can provide. Significant efforts are put in to capitalize on the potential that DBO has to address measurement accuracy and robustness. Introduction of many measurement wavelength choices (continuous wavelength) in DBO is one of the key new capabilities in this area. Along with the continuous choice of wavelengths, the algorithms (fueled by swing-curve physics) on how to use these wavelengths are of high importance for a robust recipe setup that can avoid the impact from process stack variations (symmetric as well as asymmetric). All these are discussed. Moreover, another aspect of boosting measurement accuracy and robustness is discussed that deploys the capability to combine overlay measurement data from multiple wavelength measurements. The goal is to provide a method to make overlay measurements immune from process stack variations and also to report health KPIs for every measurement. By combining measurements from multiple wavelengths, a final overlay measurement is generated. The results show a significant benefit in accuracy and robustness against process stack variation. These results are supported by both measurement data as well as simulation from many product stacks.
On-product overlay requirements are becoming more challenging with every next technology node due to the continued decrease of the device dimensions and process tolerances. Therefore, current and future technology nodes require demanding metrology capabilities such as target designs that are robust towards process variations and high overlay measurement density (e.g. for higher order process corrections) to enable advanced process control solutions. The impact of advanced control solutions based on YieldStar overlay data is being presented in this paper. Multi patterning techniques are applied for critical layers and leading to additional overlay measurement demands. The use of 1D process steps results in the need of overlay measurements relative to more than one layer. Dealing with the increased number of overlay measurements while keeping the high measurement density and metrology accuracy at the same time presents a challenge for high volume manufacturing (HVM). These challenges are addressed by the capability to measure multi-layer targets with the recently introduced YieldStar metrology tool, YS350. On-product overlay results of such multi-layers and standard targets are presented including measurement stability performance.
The optical coupling between gratings in diffraction-based overlay triggers a swing-curve1,6 like response of the target’s signal contrast and overlay sensitivity through measurement wavelengths and polarizations. This means there are distinct measurement recipes (wavelength and polarization combinations) for a given target where signal contrast and overlay sensitivity are located at the optimal parts of the swing-curve that can provide accurate and robust measurements. Some of these optimal recipes can be the ideal choices of settings for production. The user has to stay away from the non-optimal recipe choices (that are located on the undesirable parts of the swing-curve) to avoid possibilities to make overlay measurement error that can be sometimes (depending on the amount of asymmetry and stack) in the order of several “nm”. To accurately identify these optimum operating areas of the swing-curve during an experimental setup, one needs to have full-flexibility in wavelength and polarization choices. In this technical publication, a diffraction-based overlay (DBO) measurement tool with many choices of wavelengths and polarizations is utilized on advanced production stacks to study swing-curves. Results show that depending on the stack and the presence of asymmetry, the swing behavior can significantly vary and a solid procedure is needed to identify a recipe during setup that is robust against variations in stack and grating asymmetry. An approach is discussed on how to use this knowledge of swing-curve to identify recipe that is not only accurate at setup, but also robust over the wafer, and wafer-to-wafer. KPIs are reported in run-time to ensure the quality / accuracy of the reading (basically acting as an error bar to overlay measurement).
In order to meet current and future node overlay, CD and focus requirements, metrology and process control performance need to be continuously improved. In addition, more complex lithography techniques, such as double patterning, advanced device designs, such as FinFET, as well as advanced materials like hardmasks, pose new challenges for metrology and process control. In this publication several systematic steps are taken to face these challenges.
The target size reduction for overlay metrology is driven by the optimization of the device area. Furthermore, for the
future semiconductor nodes accurate metrology on the order of 0.2 nm is necessary locally in the device area, requiring
small in-die targets that fit within the product structures on the wafer. In this, the diffraction-based overlay metrology
using optical scatterometry is challenged to extreme limits. The small grating cannot be considered as an infinitely
repeating line-space structure with a sharply peaked spectrum, however a continuous spectrum is observed. Also,
metrology proximity effects due to the environment near the metrology target need to be taken into account. On the one
hand, this sets strict design and assembly rules of the metrology sensor. On the other hand, the optical ray-based analysis
is extended to wave-based analysis to capture the full extent of the overlay application and sensor. In this publication, the
challenges of sub-nanometer in-die overlay metrology are addressed, including measurements and simulations.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Time metrology, Chemical mechanical planarization, Scanners, Diffraction, Thin film coatings, Tin, High volume manufacturing
Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.
Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor
manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are
presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction
efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO
targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference
targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty
values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate
metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay
metrology.
There is no overlay standard in the world. For critical dimension (CD), we may use the VLSI standard or programmed
pitch offsets to determine the CD accuracy or CD sensitivity. Programmed overlay offsets can provide relatively accurate
sub-nanometer level overlay splits but it is only on a single layer and does not contain layer-to-layer process variations.
The splits of scanner magnification can check the trend of overlay sensitivity but it cannot provide the exact value of
overlay offsets. Transmission electron microscopes (TEM) can be used as a final overly error verification tool. However,
TEM sample preparation for after-development-inspection (ADI) will introduce even more sample distortion errors.
Therefore, unlike CD metrology, there is no clean and systematic way to verify the accuracy of overlay metrology. These
technical barriers necessitate matching diffraction-based overlay and image-based overlay, especially for sub-nanometer
point-to-point matching requirement.
In this paper, we compare the correlation of ADI to after-etch-inspection (AEI) by using image-based box-in-box overlay
measurement and diffraction-based overlay measurement on the same wafer. The ADI-to-AEI overlay data consistency
plays a key role for lithography overlay APC success and AEI overlay should be treated as the final standard for overlay
accuracy. We found that process-induced asymmetric profiles of overlay marks will lead to ADI-to-AEI overlay bias.
This bias is proportional to the degree of profile asymmetry and different color/wavelength have different sensitivity to
this ADI-to-AEI bias.
Our experimental results show that the ADI-to-AEI overlay data bias can indeed be significantly improved by selecting
the color/wavelength with minimum sensitivity to the asymmetry profile. These results make us believe that overlay
metrology recipe setup is quite critical no matter for image-based overlay or diffraction-based overlay. Otherwise,
problematic overlay data will be taken into APC feedback loop and lead to wrong overlay correction.
For the 28 nm node lithographic production steps, the process window for both overlay and CD are becoming
increasingly tight. The overlay stability of lithography tools must be at a level of 1-2 nm within the product cycle time,
while focus needs to be stable within 5 nm. Well-matched tools are crucial to improve the flexibility of tool usage and
the pressure for higher tool availability is allowing less time for periodic maintenance and tool recovery. Here, we
describe the way of working and results obtained with a long-term stability control application, containing a scanner
performance control system with a correction feedback loop deploying scatterometry. In this study the overlay
performance for immersion scanners was stabilized and the point-to-point difference to a reference is maintained at less
than 4 nm. The capability of tool recovery handling after interventions is demonstrated. Results of overlay matching
between machines are shown. The tool stability for focus was controlled in a range of less than 5 nm while improving the
total focus uniformity.
Improved overlay performance is one of the critical elements in enabling the continuing advancement of the
semiconductor integrated circuit (IC) industry. With each advancing process node, additional sources of overlay error
and new methods of reducing those errors need to be taken into account. We consider the impact of mask registration or
pattern placement errors on intra-field on-wafer overlay performance. Mask registration data is typically minimally
sampled and not well incorporated into the wafer fab overlay systems. In this work we consider mask-to-mask overlay
and point out the importance of high density sampling as well as the potential for improved mask qualification and
disposition.
KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Scanners, Back end of line, Lithography, 3D metrology, Finite element methods, Scatterometry, Critical dimension metrology
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput).
Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at
ASML. Authors have already published results of a thorough investigation of this promising new metrology
technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and
advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from
YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications.
Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.
KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Scanners, Lithography, Back end of line, Metals, Scatterometry, Front end of line, Signal to noise ratio
Advanced lithography is becoming increasingly demanding when speed and sophistication in communication
between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all
measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and
matching needs in to deep sub-nanometer level [4].
Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have
already published results of a thorough investigation of this promising new metrology technique which showed
excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for
CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform.
This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus)
and product wafer applications.
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