This paper first introduces the application background of detection and processing integrated intelligent image sensor, and proposes an overall architecture of intelligent image sensor that uses hybrid stacking process for vertical interconnection. Among them, the top pixel layer mainly contains 10K×10K 5um pixel array and row and column drive array, which gives the pixel structure, simulates and analyzes the pixel noise index and effectively guides the design of the readout circuit structure. The lower chip layer mainly contains readout circuits, image signal processing ISPs, general-purpose CPU units, AI neural processing units, and on-chip SRAM. The image signal processing ISP function and the AI neural processing unit are introduced in detail, and the FPGA verification results of the AI neural processing unit are given.
This paper first introduces the application background of detection and processing integrated intelligent image sensor and proposes an overall architecture of intelligent image sensor that uses hybrid stacking process for vertical interconnection. Among them, the top pixel layer mainly contains 10K×10K 5 um pixel array and row and column drive array, which gives the pixel structure, simulates and analyzes the pixel noise index and effectively guides the design of the readout circuit structure. The lower chip layer mainly contains readout circuits, image signal processing ISPs, general-purpose CPU units, AI neural processing units, and on-chip SRAM. The image signal processing ISP function and the AI neural processing unit are introduced in detail, and the FPGA verification results of the AI neural processing unit are given.
A full-sky autonomous star map identification algorithm based on radial and cyclic features is proposed. The algorithm defines a star pattern, composed of radial angular distances and circular angles. Then, a three-step strategy is adopted to find the correspondence of the sensor pattern and the catalog pattern, including initial lookup table match, cyclic dynamic match, and validation. A number of experiments are carried out on simulated and real star images. The simulation results show that the proposed method provides improved performance, especially on robustness against up to 6 false stars. Also, the average identification time is about 45ms, and memory requirement is 16MB, having a good satisfaction to the requirements of the target system.
The Low level light sensor has evolved from early ICCD device to EMCCD that appeared at the beginning of this century. With the continuous progress of CMOS technology, the scientific CMOS sensors were developed, which have been used for industrial cameras in high sensitivity imaging. This article described a low level light CMOS detector and its associated camera, which were developed by Beijing Institute of Space Mechanics and Electricity (BISME) in cooperation with a domestic detector manufacturer. We had an in-depth discussion of the chip's high sensitivity design techniques and analyze the weak charge transfer optimization mechanism. Then both the CMOS and EMCCD detector were combined with lens and video processing circuits to conduct a laboratorial test, finally low light detection performance of them were compared and analyzed. The SNR of CMOS imaging circuits was basically equal to the EMCCD imaging circuits when the camera's entrance pupil radiance was less than 0.5E-05 W/m2 /sr, when the radiance was up to 2E-05 W/m2 /sr, the SNR of CMOS circuits was about 2dB better than the EMCCD circuits.
Abstract—a non-uniformity correction algorithm is proposed and implemented on a Field-Programmable Gate Array (FPGA) hardware platform to solve a problem of pixel response non-uniformity(PRNU) for multiple Time Delay and Integration Charge Couple Device(TDICCD) camera. The non-uniformity is introduced and a synthetical correction algorithm is presented, in which the two-point correction method is applied to a single channel, gain averaging correction method among multi-channel and scene-adaptive correction method among multiple-TDICCD. Then, the correction algorithm is generated. Finally, the FPGA ability for fix-point processing is analyzed; the correction algorithm is optimized, and implemented on FPGA. Testing results indicate that the non-uniformity can be decreased from 8.27% to 0.51% for three TDICCDs camera's images with this proposed correction algorithm, proving that this correction algorithm is with high real-time performance, great engineering realization and satisfaction for the system requirements.
A multi-spectral time delay and integration charge couple device(TDICCD) focal plane imaging and processing system is introduced in this paper. FPGA is the core logic control of the system. The main hardware component of the system and the implementation method of FPGA are described and the diagrams of main modules are presented. Software workflow and a variety of image processing methods are also given. Test results show that the design achieves data transfer speed of 4.48Gbps and realizes real-time processing of image for high-speed multi-channel TDICCD camera so that meets the system requirement.
A non-uniformity correction algorithm is proposed and implemented on a Field-Programmable Gate Array (FPGA) hardware platform to solve a pixel response non-uniformity(PRNU) problem of multi Time Delay and Integration Charge Couple Device(TDICCD) camera. The non-uniformity are introduced and the synthetical correction algorithm is presented, in which the two-point correction method is used in a single channel, gain averaging correction method among multi-channel and the sceneadaptive correction method among multi-TDICCD. Then, the correction algorithm is designed. Finally, analyzing the FPGA ability for fix-point processing, the correction algorithm is optimized, and implemented on FPGA. Testing results indicate that the non-uniformity can be decreased from 8.27% to 0.51% for three TDICCDs camera's images with the proposed correction algorithm, proving that this correction algorithm is with high real-time performance, great engineering realization and satisfaction for the system requirements.
KEYWORDS: Image processing, Field programmable gate arrays, Imaging systems, Cameras, Control systems, Image acquisition, Digital image processing, Digital signal processing, Nonuniformity corrections, Clocks
A high-speed multi-channel multi time delay and integration charge couple device(TDICCD) image acquisition and processing system is introduced in this paper. FPGA is the core logic control of the system. The main hardware component of the system and the implementation method of FPGA are described and the diagrams of main modules are presented. Software workflow and a variety of image processing methods are also given. Test results show that the design achieves data transfer speed of 2.4Gbps and realizes real-time processing of image for high-speed multi-channel TDICCD camera so that meets the system requirement.
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