KEYWORDS: Manufacturing, Computer aided design, Design for manufacturability, Design for manufacturing, Process control, Semiconducting wafers, Control systems, Transistors, Metrology, Chemical elements
Transistor dimensions are quickly approaching atomic levels. Metrology is already a challenge. Several technologies
have evolved to keep pace such as scatterometry and bare wafer inspection. Lithography critical dimensions, registration
and pitch are the forefront of dimensional scaling challenges. Variability at these dimensions can limit function,
performance, yield and profitability with design for manufacturing (DFM) challenges. Intel's integrated device
manufacturing (IDM) model has enabled many technologies and disciplines to come together to provide the most cost
effective and optimal solutions to Moore's law scaling challenges. Intel's Automated Manufacturing Technology (AMT)
capabilities play a significant role in enabling optimal Moore's law scaling solutions. The information turn cycle starts
with the definition of the technology Test Chip and ends with the analysis of results from end of line (EOL) metrology.
We will discuss the relevant DFM elements of AMT to enable: test-chip setup, computational lithography and
validation, product & process modeling and setup, intelligence and control to minimize variability, rapid yield learning,
and rapid product design learning.
KEYWORDS: Process control, Data modeling, Control systems, Semiconducting wafers, Standards development, Computer architecture, System integration, Manufacturing, Statistical analysis, Databases
Process Control Systems (PCS) are becoming more crucial to the success of Integrated Circuit makers due to their direct impact on product quality, cost, and Fab output. The primary objective of PCS is to minimize variability by detecting and correcting non optimal performance. Current PCS implementations are considered disparate, where each PCS application is designed, deployed and supported separately. Each implementation targets a specific area of control such as equipment performance, wafer manufacturing, and process health monitoring. With Intel entering the nanometer technology era, tighter process specifications are required for higher yields and lower cost. This requires areas of control to be tightly coupled and integrated to achieve the optimal performance. This requirement can be achieved via consistent design and deployment of the integrated PCS. PCS integration will result in several benefits such as leveraging commonalities, avoiding redundancy, and facilitating sharing between implementations. This paper will address PCS implementations and focus on benefits and requirements of the integrated PCS. Intel integrated PCS Architecture will be then presented and its components will be briefly discussed. Finally, industry direction and efforts to standardize PCS interfaces that enable PCS integration will be presented.
This paper presents a novel methodology for designing a 2D multiscale feature detector, which consists of a filter bank and a maximum a posteriori (MAP) classifier. The framework assumes the availability of a one-scale filter with a particular indicator response to the desired feature. This filter is used to generate a multiscale set of discrete filters by sampling on a rectangular lattice to preserve the indicator responses at all the scales. The net step in the framework consists of designing the filter bank to approximate the generated filters. A 2D MAP detector is then designed to minimize detection errors. With the assumption of known feature, the resulting detector depends only on the filter bank, and not on the noise. Relaxing this assumption yields a detection algorithm that is noise dependent and computationally intensive. The framework is applied to edge detection in a noisy environment, and the results indicate efficient detection. Moreover the 2D MAP can find feature end-points by direct processing of the image. This is unlike conventional methods where edges need to be first detected and then processed to locate the corners. Examples are presented to demonstrate the algorithm.
We have developed a vision application using the IDASTM (imaging development and applciation system) real-time image processing system to inspect discrete stamped metal parts. Specifically, the stamped clutch plates coming through the manufacturing line at speeds higher than 6000 parts per hour are to be inspected for defects on both surfaces of the clutch plate as well as defects on the profile of the clutch plate with dimensional accuracy in mils. The conventional area scan approach will not be practical die to the resolution requirements and the processing speed. We have developed a solution based on a 2048 CCD linescan camera and a conveyor system to transport the plates under the camera. This real-time multitasking system deals with all the complexities one normally encounters during the implementation of a real-time machine vision system. This paper will describe the application and the design strategies that made the solution both practical and economical.
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