Mask inspection tool with DUV laser source has been used for Photo-mask production in many years due to its high sensitivity, high throughput, and good CoO. Due to the advance of NGL technology such as EUVL and Nano-imprint lithography (NIL), there is a demand for extending inspection capability for DUV mask inspection tool for the minute pattern such as hp4xnm or less. But current DUV inspection tool has sensitivity constrain for the minute pattern since inspection optics has the resolution limit determined by the inspection wavelength and optics NA.
Based on the unresolved pattern inspection capability study using DUV mask inspection tool NPI-7000 for 14nm/10nm technology nodes, we developed a new optical imaging method and tested its inspection capability for the minute pattern smaller than the optical resolution. We confirmed the excellent defect detection capability and the expendability of DUV optics inspection using the new inspection method. Here, the inspection result of unresolved hp26/20nm pattern obtained by NPI-7000 with the new inspection method is descried.
Various technologies such as multiple patterning (MP) are being developed to extend the current DUV optical
lithography to deal with the delay of next generation lithography such as EUV and NIL. Likewise, it is necessary to
continue to develop technologies for mask inspection tools for masks fabricated for the DUV optical lithography so that
they can be appropriately inspected, until the next generation EB or EUV actinic inspection tools is put into practical use.
To fabricate 1x nm devices with the present lithography process, the industry will likely further extend double
patterning (DP) to multiple patterning (MP). For MP, the requirements for the inspection sensitivity of traditional defects
such as intrusions or extrusions do not change much, but those for CD control and overlay tolerances will become more
critical.
In this paper, we will discuss the main features of NPI-7000, a DUV based mask inspection tool for the 1x nm node
devices, and our challenges in enhancing the CD error sensitivities to enable the inspection of masks.
Through the four years of study in Association of Super-Advanced Electronics Technologies (ASET) on reducing mask
manufacturing Turn Around Time (TAT) and cost, we have been able to establish a technology to improve the efficiency
of the review process by applying a printability verification function that utilizes computational lithography simulations
to analyze defects detected by a high-resolution mask inspection system. With the advent of Source-Mask Optimization
(SMO) and other technologies that extend the life of existing optical lithography, it is becoming extremely difficult to
judge a defect only by the shape of a mask pattern, while avoiding pseudo-defects. Thus, printability verification is
indispensable for filtering out nuisance defects from high-resolution mask inspection results.
When using computational lithography simulations to verify printability with high precision, the image captured by the
inspection system must be prepared with extensive care. However, for practical applications, this preparation process
needs to be simplified. In addition, utilizing Mask Data Rank (MDR) to vary the defect detection sensitivity according to
the patterns is also useful for simultaneously inspecting minute patterns and avoiding pseudo-defects. Combining these
two technologies, we believe practical mask inspection for next generation lithography is achievable.
We have been improving the estimation accuracy of the printability verification function through discussion with several
customers and evaluation of their masks. In this report, we will describe the progress of these practical mask verification
functions developed through customers' evaluations.
We report on the development of a new mask inspection technology that makes total inspection faster and less costly.
The new technology adopts a method of selecting a defect detection sensitivity level for every local area, defined by
factors such as defect judgment algorithm and defect judgment threshold. This approach results in a reduction of pseudodefect
count leading to shorter inspection and review time. Selected defect detection sensitivity levels for every local
area are extracted from a database of Mask Data Rank (MDR) that is based on the design intent from the design stage,
and/or on a pre-analysis of inspection pattern data. The proposed system also executes a printability verification
function, not only for the mask defect regions but also for specific portions where high Mask Error Enhancement Factor
(MEEF) is determined. It is necessary to ascertain suppression of pseudo-defect detection for extremely complicated
masks such as masks with Source-Mask Optimization (SMO). This work reports on the new mask inspection system.
With continued shrinkage of the semiconductor technology node, the inspection of mask with a single preset defect
detection sensitivity level becomes impractical because of the increase occurrence of false capturing of defects.
Inspection of leading-edge masks with conventional defect detection method, redundant detection of defects such as
pseudo defects, or anomalies such as slightly deformed OPCs caused by assist features tend to increase the Turn Around
Time (TAT) and cost of ownership (COO).
This report describes a new method for the inspection of mask. It assigns defect detection sensitivity levels to local area
inspections and is named as Regional Sensitivity Applied Inspection (RSAI). Then, the sensitivity information from each
local area is converted into a format that can be fed into a Mask Data Rank (MDR) which is represented on the basis of
pattern prioritization determined at the device design stage. Core technologies employing this concept resulted in the
shortening of TAT where samples of actual device mask patterns were used.
Printability verification functions (PVF) were applied to the advancement of technologies such as to Source Mask
Optimization (SMO) technology. We report on the shortening of TAT that was achieved by the implementation of a new
inspection technology that combines RSAI with MDR, and employs printability verification functions.
In addition to the conventional demands for high sensitivities with which the mask inspection system detects the minute
size defects, capability to extract true defects from a wide variety of patterns that should not be counted as pseudo
defects has been quite demanding. It is necessary to ascertain suppression of MEEF incurred by the combination of
parameters such as LER and defects of SRAF.
NFT and Brion are jointly developing a mask-image based printability verification system with functions combining
their respective technologies with the results from ASET's research. This report describes such defect detection results
and introduces the development of a mask inspection system with printability verification function.
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection results on test and production reticles have been validated with AIMSTM.
The cost of mask is increasing dramatically along with the continuous semiconductor scaling.
ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask
Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the
New Energy and Industrial Technology Development Organization (NEDO). Concerning the mask
inspection, the project aims at shortening the review time after inspection.
In mask inspection it approaches the limit to inspect the entire surface of a mask in the unique
defect judgment algorithm without a pseudo defect. In addition, a nuisance defect including a
pseudo defect increases by raising the defect detection sensitivity, and the review time after
inspection increases. Mask inspection total time increases too and this will raise the mask inspection
cost.
Practical mask inspection can be conducted now by inputting the judgment level based on
directions of design data there and by making a defect judgment level of every domestic area
changeable.
We can also shorten the review time by analyzing the printability on the wafer of the detected
defect by the simulation, and by using the result for the defect judgment.
In this report, we will show the latest research result about an inspection system technology that
the defect judgment level for each domestic area can be changed, and a method to input the defect
judgment level based on the pattern importance, which a device designer intended, into inspection
equipment. In addition, we will show a design of the interface technology that hand over the
information of the detected defect to a process simulator (wafer image simulator).
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection result has been validated with AIMSTM.
In this paper we present the method that NuFlare photomask inspection systems can use to strongly reduce
pseudo detections by use of TK-CMI software. The NuFlare inspection system is capable to detect the
smallest defects in the 45 and 32-nm nodes and has recently been introduced to production. It links up with
a compute cluster with Takumi's Criticality-Marker Information software (TK-CMI). TK-CMI quickly analyzes
the ~200GB post-OPC layout or multi-layer pre-OPC layout and assigns various types of criticality regions.
The basic set of criticalities is made to address the challenges that typical maskmakers experience. The TKCMI
system also supports design-intent-based criticalities. The NuFlare inspection system uses this full-mask
criticality information and generates flexible inspection recipes that inspect low-criticality areas with relaxed
sensitivity resulting in reduction of pseudo detections in such regions.
The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET
started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation
(MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial
Technology Development Organization (NEDO).
We report on the development of a new low cost mask inspection technology with short Turn Around
Time (TAT), as a result of adopting a method of selecting defect detection sensitivity level for every local
area, defined by such factors as defect judgment algorithm and defect judgment threshold, as one of the
pseudo-defect-reduction technique necessary to shorten mask inspection TAT. Those factors are extracted
from the database of Mask Data Rank (MDR) and converted on the basis of pattern prioritization determined at device design stage, using parallel computation.
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