Design, fabrication and assembly of curved imaging arrays is challenging. Optical design theory reveals the design challenge of a well-corrected image across a planar surface. As the field of view (FOV) is increased, deviation from the plane of best focus (Petzval surface) is increased. Reducing that deviation drives the power of lens elements higher, resulting in the increase of residual aberrations, especially zonal spherical aberrations. Wide FOV systems having customary planar focal plane arrays (FPA) require additional lenses to correct for distortions. The curved nature of a hemispherical imager minimizes off-axis aberrations and distortions throughout the FOV, and thus is of significant interest for increasing system performance while also reducing complexity, SWAP and cost. This paper will present an overview of hemispherical array development enabled by Quilt Packaging (QP) chip integration technology for creation of piece-wise curved arrays. QP is a direct edge-to-edge chip interconnection approach that can be implemented to enable hemispherical imagers created from the piecewise integration of 2D array ICs of varying geometries. The unique attributes of QP allow for an interconnection that is both robust mechanically and very low loss, high bandwidth electrically. Utilizing this approach allows for straightforward 2D wafer processing and design, reduces or eliminates the need for thinning/flexible chips, and can improve fabrication yields by reducing individual chip area. Indiana Integrated Circuits, LLC and Northrop Grumman Corporation are evaluating the potential performance, reliability and SWAP benefits of extending earlier Quilt Packaging imager work into the 3rd dimension for curved arrays.
Several new technologies have been developed over recent years that make a fundamental change in the scene projection for infrared hardware in the loop test. Namely many of the innovations are in Read In Integrated Circuit (RIIC) architecture, which can lead to an operational and cost effective solution for producing large emitter arrays based on the assembly of smaller sub-arrays. Array sizes of 2048x2048 and larger are required to meet the high fidelity test needs of today’s modern infrared sensors. The Test Resource Management Center (TRMC) Test and Evaluation/Science and Technology (T and E/S and T) Program through the U.S. Army Program Executive Office for Simulation, Training and Instrumentations (PEO STRI) has contracted with SBIR and its partners to investigate integrating new technologies in order to achieve array sizes much larger than are available today. SBIR and its partners have undertaken several proof-of-concept experiments that provide the groundwork for producing a tiled emitter array. Herein we will report on the results of these experiments, including the demonstration of edge connections formed between different ICs with a gap of less than 10µm.
We present Finite-Difference Time-Domain (FDTD) simulations to explore feasibility of chip-to-chip waveguide
coupling via Optical Quilt Packaging (OQP). OQP is a newly proposed scheme for wide-bandwidth, highly-efficient
waveguide coupling and is suitable for direct optical interconnect between semiconductor optical sources, optical
waveguides, and detectors via waveguides. This approach leverages advances in quilt packaging (QP), an electronic
packaging technique wherein contacts formed along the vertical faces are joined to form electrically-conductive and
mechanically-stable chip-to-chip contacts. In OQP, waveguides of separate substrates are aligned with sub-micron
accuracy by protruding lithographically-defined copper nodules on the side of a chip. With OQP, high efficiency chip-to-chip
optical coupling can be achieved by aligning waveguides of separate chips with sub-micron accuracy and reducing
chip-to-chip distance. We used MEEP (MIT Electromagnetic Equation Propagation) to investigate the feasibility of OQP
by calculating the optical coupling loss between butt coupled waveguides. Transmission between a typical QCL ridge
waveguide and a single-mode Ge-on-Si waveguide was calculated to exceed 65% when an interchip gap of 0.5 μm and
to be no worse than 20% for a gap of less than 4 μm. These results compare favorably to conventional off-chip coupling.
To further increase the coupling efficiency and reduce sensitivity to alignment, we used a horn-shaped Ge-on-Si
waveguide and found a 13% increase in coupling efficiency when the horn is 1.5 times wider than the wavelength and 2
times longer than the wavelength. Also when the horizontal misalignment increases, coupling loss of the horn-shaped
waveguide increases at a slower rate than a ridge waveguide.
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