As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.
As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask
Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and
CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process.
However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that the classical mask CD
metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at
advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution
assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity.
These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced
characterization methods in order to optimize the mask process to meet the wafer lithographer’s needs. These advanced
characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot
analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled
wafer performance.
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask
manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography
Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the
new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex
mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements
over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature
resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible
solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for
10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.
According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy.
Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.
In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.
The Critical Dimension Uniformity (CDU) specification on photomasks continues to decrease with each successive node.
The ITRS roadmap for optical masks indicates that the CDU (3 sigma) for dense lines on binary or attenuated phase shift
mask is 3.4nm for the 45nm half-pitch (45HP) node and will decrease to 2.4nm for the 32HP node. The current
capability of leading-edge mask shop patterning processes results in CDU variation across the photomask of a similar
magnitude.
Hence, we are entering a phase where the mask CDU specification is approaching the limit of the capability of the
current Process of Record (POR). Mask shops have started exploring more active mechanisms to improve the CDU
capability of the mask process. A typical application is feeding back the CDU data to adjust the mask writer dose to
compensate for non-uniformity in the CDs, resulting in improved quality of subsequent masks. Mask makers are
currently using the CD-SEM tool for this application. While the resolution of SEM data ensures its position as the
industry standard and continued requirement to establish the photomask CD Mean to Target value, a dense measurement
of CDs across the reticle with minimal cycle time impact would have value.
In this paper, we describe the basic theory and application of a new, reticle inspection intensity-based CDU approach
that has the advantage of dense sampling over larger areas on the mask. The TeraScanHR high NA reticle inspection
system is used in this study; it can scan the entire reticle at relatively high throughput, and is ideally suited for collecting
dense CDU data. We describe results obtained on advanced memory masks and discuss applications of CDU maps for
optimizing the mask manufacturing process. A reticle inspection map of CDU is complementary to CD-SEM data. The
dense data set has value for various applications, including feedback to mask writer and engineering analysis within the
mask shop.
Conventional photomask inspection techniques utilize global sensitivity for all inspected area in the die; SRAF and OPC
features become the sensitivity-limiters for advanced photomasks which can result in reduced sensitivity to defects of
interest (DOI). We describe the implementation of Sensitivity Control Layer (SCL), a novel database inspection
methodology for the KLA-Tencor TerascanHR platform to improve sensitivity and reduce nuisance detections. This
methodology enables inspection at maximum sensitivity in critical die-areas via "layer definition" and reducing
sensitivity to sub-resolution features during inspection which can dramatically improve false-rate. DRAM and FLASH
inspection performance was improved through the use of up to 6-control layers to increase sensitivity in the active area
while reducing false detections by as much as 100X. Post-inspection defect analysis, and improved disposition accuracy
of the SCL-enabled inspections will also benefit cycle time and higher throughput. In all test cases, sensitivity
parameters were increased in the regions of interest over baseline inspections run with typical, production-type
inspection methodologies. SCL inspection-sensitivity management, and layer partitioning of OPC structures, SRAF's,
and other sub-resolution features is discussed in detail.
The authors are reporting on the comparison of various industry methods of managing, controlling and limiting haze
growth on 193nm reticles. This comparison includes reporting on the results from the Reticle Haze Treatment (RigHT)
process developed at Micron / Photronics Mask Technology Center and transferred to Photronics, Inc. This process
provides 193nm PSM reticles that have shown no haze growth after excessive wafer exposures and are usable for the life
of the reticle.
Conventional photomask inspection techniques utilize global sensitivity for all inspected area in the die; SRAF and OPC
features become the sensitivity-limiters, which can result in reduced visibility to defects of interest (DOI). We describe
the implementation of Sensitivity Control Layer (SCL), a novel database inspection methodology for the KLA-Tencor
TerascanHR platform. This methodology enables inspection at maximum sensitivity in critical die-areas via "layer
definition" during job set-up and sensitivity management of the layers during inspection. Memory device inspection
performance was improved through the use of up to six control layers to increase sensitivity in the active area while
reducing nuisance detections by as much as 100X. The corresponding inspection time was reduced by 30%, illustrating
the potential for substantial throughput advantage using SCL. Post-inspection analysis and improved disposition
accuracy of the SCL-enabled inspections will also benefit cycle time and higher throughput. In all test cases, sensitivity
parameters were increased in the regions of interest over baseline inspections run with typical production-use
methodologies. SCL inspection management and application on OPC structures, SRAFs, and MRC violations (slivers)
are discussed in detail.
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