We fabricated sub-50-nm pitch reference grating with positional identification mark
for specifying the location. The address mark of silicon groove was fabricated by EB
lithography and dry etching processes. The sub-50-nm pitch multilayer substrate was
bonded with the address mark silicon substrate and polished as a flat chip. Next the fine
pitch grating reference pattern was fabricated by SiO2 selective chemical etching.
Finally the sub-50-nm pitch grating pattern was set on the flat surface for CD-SEM due
to retarding bias system for low voltage inspection. As a result of the fundamental
characteristics evaluation using CD-SEM, the uniformity of the pitch size in the
reference chip was smaller than 1 nm in 3σ. The positional identification marks are
useful for obtaining accurate calibrations by specifying the location of the grating and
the number of calibrations. Also, the pitch-size was obtained by diffraction angle
measurements with a high-accuracy grazing incidence small-angle x-ray scattering
(GI-SAXS). The traceability of calibration is under vertification.
We present a novel multilayer grating pattern with a sub-50-nm pitch for critical dimension-scanning electron microscope (CD-SEM) magnification calibration as an advanced version of the conventional 100-nm pitch grating reference. A 25-nm pitch grating reference is fabricated by multilayer deposition of alternating materials and then material-selective chemical etching of the polished cross-sectional surface. A line and space pattern with 25-nm pitch is easily resolved, and a high-contrast secondary electron image of the grating pattern is obtained under 1-kV acceleration voltage using the CD-SEM. The uniformity of the 25-nm pitch of the grating is <1 nm in three standard deviations of the mean. The line-edge roughness of the grating pattern is also <0.5 nm. Such a fine and uniform grating pattern will fulfill the requirements of a magnification calibration reference for a next-generation CD-SEM.
We have developed a 25-nm pitch multilayer grating pattern for CD-SEM magnification
calibration instead of the conventional 100-nm pitch grating reference. The 25-nm pitch
grating reference was fabricated by multilayer deposition of alternative alternating SiO2 and Si layers and then the reference chip was fabricated by substrate bonding and
polishing process. Finally the 25-nm pitch grating pattern was achieved using the material-selective chemical etching of the polished cross-sectional surface. We
evaluated the 25-nm pitch grating reference chip using CD-SEM. A high-contrast
secondary electron image of the grating pattern was obtained under 1-kV acceleration
voltage. The uniformity of the 25-nm pitch size of the grating was less than 1 nm in 3σ.
The line edge roughness of the grating pattern was also less than 1 nm. Such a fine and
uniform grating pattern will fulfill the requirements of a magnification calibration reference for next-generation CD-SEM.
We have developed a novel multi-layer grating pattern with a sub-50-nm pitch
size for CD-SEM magnification calibration instead of the conventional 100-nm pitch
grating reference. The sub-50-nm pitch size grating reference was fabricated by
multi-layer deposition of alternative two alternating materials and then the
material-selective chemical etching of the cleaved cross-sectional surface. A line and
space pattern with 10-nm pitch size was easily resolved and a high-contrast secondary
electron image of the grating pattern was obtained under 1-kV acceleration voltage
using CD-SEM. The uniformity of the 20-nm pitch size of the grating was less than 1
nm in 3σ. The line edge roughness of the grating pattern was also less than 1 nm. Such a
fine and uniform grating pattern will fulfill the requirements of a magnification
calibration reference for next-generation CD-SEM.
KEYWORDS: Line edge roughness, Smoothing, Scanning electron microscopy, Samarium, Image processing, Image analysis, Signal processing, Line width roughness, Electron microscopes, Interference (communication)
The necessity for and validity of the bias-free line-edge roughness (LER) evaluation are examined. In a typical case,
the LER obtained by the conventional method is found to contain 10% or more bias caused by noise. That is, the biasfree
LER evaluation is needed to achieve absolute measurements. The bias-free method is also shown to be necessary in
relative LER measurements. Moreover, the impact of the smoothing (i.e., averaging the signal intensity in x-direction)
process on the LER obtained from scanning electron microscope (SEM) image was evaluated quantitatively by using
the bias-free LER evaluation algorithm. We found that the smoothing broadens the SEM signal profile and causes a
change in the LER value. Under practical conditions, his smoothing-induced LER change was 0.4 nm in the sample
used for this study. This can be a large error when measuring a small LER. Finally, a procedure for optimizing the
smoothing number used for applying the bias-free LER application was proposed by considering the validity limit of the
application and smoothing-induced LER change.
KEYWORDS: Line edge roughness, Line width roughness, Copper, Semiconducting wafers, Dielectrics, Diffusion, Metals, Scanning electron microscopy, Reliability, Analytical research
To establish a method for measuring interconnect line-edge roughness (LER), low-k line patterns were observed and
electric-field concentration was simulated based on the observation results. Wedges were observed on the edges, and the
bottom and the top widths of the average wedge feature were 60 nm and 7 nm (or smaller), respectively. Simulation
showed that the LER causes serious degradation of TDDB immunity at 100-nm-pitch Cu/low-k interconnects. The
maximum electric-field intensity depends upon the conventional LER metric, 3Rq, but depends more strongly on the
wedge angle, the curvature of the tip, and the minimum linewidth.
Electron projection lithography (EPL) has high-resolution capability of meeting the 65 nm technology node and beyond. A first-generation EPL has been developed and improved at Nikon and Selete. Defect free mask is indispensable for successful introduction of this technology into the production stage. However, an EPL mask is considerably different from today's optical photomask, especially due to its 3-D structure. Hence the conventional methods of quality assurance used for optical photomask are not applicable for EPL mask. Selete is now developing a series of defect inspection and repair systems for an EPL stencil mask infrastructure. In our previous work we reported on the individual systems for defect inspection and mask repair by using programmed defects. Moreover, we verified a number of the defect inspection and repair systems through a sequential process. In this work the motivation is to investigate relationship issues among these tools for future applications, such as defect printability, CD controllability, calibration, optimization, performance matching, and automated operation.
KEYWORDS: Metals, Transmission electron microscopy, Lithography, Scanners, Copper, Scanning electron microscopy, Resistance, Electron beam lithography, Overlay metrology, Chemical mechanical planarization
We evaluate electron projection lithography (EPL) performance for a via layer at 65-nm and 45-nm technology nodes through the fabrication of a via-chain test element group (TEG) using EPL/ArF mix-and-match (M&M) lithography. The via-chain is prepared by tow-layer metallization using a Cu/low-k single damascene process. Here, Metal 1 (M1) and Metal 2 (M2) are patterned by using an ArF scanner, and Via 1 (V1) is patterned by using an EPL exposure system. For the EPL performance evaluation at 65-nm technology node, we utilized transmission electron microscope (TEM) and confirmed that a 100-nm via-chain is successfully fabricated and a yield of 94% is achieved. For an EPL performance evaluation at 45-nm technology node, also by using TEM, we confirmed that fabrication of a 70-nm via-chain with reasonable quality is feasible although with a lower yield. For our next step we are planning to carry out an EPL performance at 32-nm technology node by printing a via layer and a metal layer using a corresponding via-chain TEG. Here, M1, V1 and M2 will be patterned by using the EPL exposure system. Although an EPL development at 32-nm technology node is still at its early stages, a via-hole resist pattern of 50 nm and a lines and spaces (L/S) resist pattern of 45 nm have almost been completed. These results suggest that EPL is quite promising for meeting the back-end-of-line (BEOL) process requirement for 65-nm, 45-nm and also for 32-nm technology nodes.
Selete is developing a series of defect inspection and repair systems for electron projection lithography (EPL) stencil mask infrastructure, that includes tools and software development, and also verification by EPL exposure systems. The work is carried out in collaboration with Dai Nippon Printing, Toppan Printing and HOYA. A
system for defect inspection of EPL stencil mask is developed with TOKYO SEIMITSU and HOLON. Another system for defect repairs is developed with SII NanoTechnology. The performances of these systems need to be verified for their further improvement and optimization. In this paper, we verified a series of defect inspection and
repair systems through a sequential process. We can say that EPL mask infrastructure is established and our work has
made significant contribution to it.
We have studied stencil mask repair technology with focused ion beam and developed an advanced mask repair tool for electron projection lithography. There were some challenges in the stencil mask repair, which were mainly due to its 3-dimensional structure with aspect ratio more than 10. In order to solve them, we developed some key technologies with focused ion beam (FIB). The transmitted FIB detection technique is a reliable imaging method for a 3-dimensional stencil mask. This technique makes it easy to observe deep patterns of the stencil mask and to detect the process endpoint. High-aspect processing can be achieved using gas-assisted etching (GAE) for a stencil mask. GAE enables us to repair mask patterns with aspect ratio more than 50 and very steep sidewall angle within 90±1°precisely. Edge placement accuracy of the developed tool is about 14nm by manual operation. This tool is capable to achieve less than 10nm by advanced software. It was found that FIB technology had capability to satisfy required specifications for EPL mask repair.
A new inspection system for stencil mask using transmission electron beam (E-beam) has been developed to detect defects on masks for Electron Projection Lithography (EPL) and Low Energy E-beam Proximity projection Lithography (LEEPL) for 65nm design rule and beyond. For high-performance image acquisition, the combination of multi-line Time Delay integration (TDI)- CCD camera and electron optic system (EOS) have been achieved very wide field-of-view and accurate imaging in this system. In Image Processing Unit, “Multi Algorithm Processing” is used for defect detection. One of “Multi Algorithm Processing” focuses on defects at corners of patterns. This is a new and very flexible algorithm to detect corner defects. It realizes very high detection performance compared with conventional Die-To-Database inspection. The minimum detectable defect size is smaller than 1 pixel. The pixel size is 50 nm for EPL mask and 30 nm for LEEPL mask. The performance of the system also has been confirmed using resist pattern wafer inspection results after EPL and LEEPL printing.
A new mask inspection system using transmission electron beam (EB) technology is being developed to detect defects on electron projection lithography (EPL) masks with design rules of 65-nm and below. In our new system, we use the transmission EB image, multi-line Time Delayed Integration (TDI)-CCD camera, and stage scanning. The transmission EB image can detect defects hidden in stencil patterns with a very high resolution. The scanning system, combined with a high-speed image acquisition system, enables high throughput. A mganified image of the mask stencil pattern is formed on an image sensor by the electron-optic systme. The image of the stencil patterns is captured by a multi-line TDI-CCD camera and the image data is transferred to an image-processing unit composed of multi high-speed image processors. To capture an EB image, a special TDI-CCD camera was developed. The typical pixel size is 50-nm on the mask. To achieve the goal of high-speed image processing, multi-fiber cable is used to transfer the image data from the camera to the image-processor. Each image processor shares the inspection area in parallel, and performs a die-to-database comparison. Typical inspection time for a 200-nm EPL stencil mask is 4 to 5 hours. A defect of 50-nm was observed by the developing system. This inspection system will be completed in March 2004.
We investigated the defect printability of hole patterns in electron projection lithograpy (EPL) using a diamond reticle with a programmed defect pattern. The reticle was fabricated by NTT-AT and wafer exposure was performemd using Nikon's EB projection experimental column. We simulated the defect printability to udnerstand in greater detail. We found that the mask error enhancement factor (MEF) of the size shift defect category exceeded the value of one and was degraded by the amount of beam blur. On the other hand, the printability of the dot defect category was lower than the shift category. In particular, pint hole defects smaller than 100 nm were not printed. However, the defect types of under size shift, truncation, edge intrusion, and corner intrusion (they decreased the opening area), actually increased the defect size because the defect was too small for hole patterns to print. In general, the defect printability of hole patterns depends on the beam blur, and the printed error size at the hole patterns getting larger than the line patterns. We have to pay clsoer attention to the hole pattern defect than to the line patterns.
Electron projection lithography (EPL) is a promising tool for next-generation lithography. However, beam blur due to the Coulomb effect becomes significant and degrades resolution when a high beam current is used to improve throughput. Suppressing the impact of the Coulomb effect is thus necessary to make EPL a practical tool for fabricating ULSI devices. We discuss the influence of the Coulomb effect in EPL based on our experimental results obtained using a Nikon experimental EPL column. To investigate the influence of the Coulomb effect on exposure results, we prepared three kinds of mask with different opening rates to vary the beam current on a wafer over a wide rage without affecting the lens illumination. We found that the Coulomb effect decreased the dose and focus latitude, and that the optimum focus condition varied within a sub-field. Furthermore, we found that the beam blue caused by the Coulomb effect was increased by shrinkage of the rectangular pattern end. Such shrinkage is also a problem in optical lithography, and complex pattern reshaping is necessary to correct it. The shrinkage becomes greater as the beam current increased. We estimated the amount of beam blue caused by the Coulomb effect by fitting our results through an energy deposition simulation. Our overall conclusion s that pattern reshaping and low-Coulomb-effect optics will be necessary to overcome the Coulomb effect.
Stencil masks are preferable for EPL (Electron-beam Projection Lithography)from the view point of resolution because it 's free from the chromatic aberration caused by the electron energy loss in continuous membrane. However, its mechanical structure poses several concerns. Dynamic image placement (IP)accuracy is one of the essential concerns because patterns on the stencil mask are defined by free-standing Si structures. Moreover the whole pattern areas are supported by fine Si grid structures. The step-and-scan motion of EPL tools is expected to cause dynamic displacements of these fragile structures, which lead to deterioration of resolution, critical dimension (CD)and overlay (OL) accuracies. Two kinds of the dynamic displacements on an EPL stencil mask were estimated by simulations. One is the vibration of the free-standing structures and the other is the dynamic distortion of the whole pattern area. The maximum acceleration of 5 G was assumed in the simulations according to a throughput estimation. The free-standing structures are modeled into cantilever beams and both-end-fixed beams. It was found that the vibration of the structures could be suppressed below the amplitude of 1 nm by limiting the beam length. The limitations were practical ones for complementary split of mask layout. The whole pattern area was modeled into a simple grid structure. It was found that the maximum dynamic displacement was less than 7 nm. The OL accuracy was estimated including those dynamic displacements down to 35 nm node. The results show that the dynamic displacements of the EPL stencil masks would little affect the OL accuracy. The stencil mask is applicable for device fabrication at 70 nm node and below.
This paper describes the application of a low-voltage scanning electron microscope (SEM) with nanometer-level accuracy for measurement in ultra-large-scale integration (ULSI). Minimum feature sizes of integrated circuits are expected to reach the 100-nm level and below (the nanometer region) in the near future. For the lithography process under that regime, precise critical dimension (CD) control and high resolution of resist patterns will be quite important for device fabrication, because variations in pattern sizes will degrade circuit performance. Therefore, metrology with nanometer-level accuracy is required for device fabrication under the regime. Here, we report on a CD-SEM that operates at 500 V to measure patterns at the 1 Gbit level. We used the S-8840 (Hitachi) to measure holes, lines/spaces, and the calibration standard (Micro-Scale). Several voltages from 500 V to 1000 V were used for the measurements. Static variation of less than 3 nm (3(sigma) ) was obtained in the pitch measurement of the Micro- Scale regardless of the acceleration voltages. For the holes, a lower voltage provided higher accuracy in static measurements. In the nanometer region, resist-pattern sizes microscopically fluctuate to the level of 10 nm due to the polymer characteristics of the resists (nano edge roughness). We could also characterize resist-pattern fluctuations with high accuracy. We compared our measurements with those from an atomic force microscope (AFM) for nanometer-level metrology, and conclude that at present CD-SEMs are more advantageous because of their higher accuracy and throughput.
Acid-catalyzed intramolecular dehydration of phenylcarbinol is used to design highly sensitive negative resists for electron beam lithography. Of the phenylcarbinol resists evaluated in this study, the resist composed of 1,3-bis(alpha-hydroxyisopropyl)benzene (Diol-1), m/p-cresol novolak resin, and diphenyliodonium triflate (DIT) shows the best lithographic performance in terms of sensitivity and resolution. Fine 0.25-micrometer line-and-space patterns were formed by using the resist containing Diol-1 with a dose of 3.6 (mu) C/cm2 in conjunction with a 50 kV electron beam exposure system.
A high-contrast resist, called a contrast boosted resist (CBR), using a water-repellent compound that changes into hydrophilic compounds during aqueous base development has been developed for electron-beam (EB) lithography. TBAB, 1,3,5-tris(bromoacetyl)benzene, was identified as the best water-repellent compound for the CBR. A CBR composed of novolak resin, hexamethoxymethylmelamine, 1,3,5-tris(trichloromethyl)triazine as an efficient acid generator, and TBAB enables the definition of 0.225-micrometer line-and-space patterns with an exposure dose of only 2 (mu) C/cm2 using an EB writing system (acceleration voltage: 50 kV). The polarity change caused by the reaction of the TBAB with the base as well as crosslinking of the novolak resin by the TBAB are assumed to enhance the contrast in the CBR.
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