Mr. Khoi A. Phan Profile

Khoi A. Phan

Litho Project Manager at Applied Materials Inc

SPIE Involvement:

Author

Publications (17)

Proceedings Article | 16 October 2017 Presentation + Paper

Presentation + Paper

Development of amorphous silicon based EUV hardmasks through physical vapor deposition

Anuja De Silva, Yann Mignot, Luciana Meli, Scott DeVries, Yongan Xu, Indira Seshadri, Nelson Felix, Wilson Zeng, Yong Cao, Khoi Phan, Huixiong Dai, Christopher Ngai, Michael Stolfi, Daniel Diehl

Proceedings Volume 10450, 104501A (2017) https://doi.org/10.1117/12.2280607

KEYWORDS: Amorphous silicon, Optical lithography, Etching, Photoresist materials, Silicon, Head-mounted displays, Silicon films, Chemical vapor deposition, Extreme ultraviolet, Physical vapor deposition

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Proceedings Article | 17 October 2008 Paper

Paper

Challenges for the quality control of assist features for 45nm node technology and beyond

Lin Wang, Todd Lukanc, Makoto Takahashi, Hung-Eil Kim, Khoi Phan, Taichi Yamazaki, Yosuke Kojima, Wataru Nozaki, Takashi Haraguchi, Yoshimitsu Okuda

Proceedings Volume 7122, 71220Z (2008) https://doi.org/10.1117/12.800916

KEYWORDS: Critical dimension metrology, Photomasks, Semiconducting wafers, Optical proximity correction, Line edge roughness, Chromium, Photoresist processing, Resolution enhancement technologies, Reticles, SRAF

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Proceedings Article | 5 November 2005 Paper

Paper

Haze prevention and phase/transmission preservation through cleaning process optimization

Jennifer Qin, Yuan Zhang, Rob Delgado, Barry Rockwell, Florence Tan, Khoi Phan, Lothar Berger, Min Liu, Uwe Dietez

Proceedings Volume 5992, 59921E (2005) https://doi.org/10.1117/12.633170

KEYWORDS: Reticles, Photomasks, Air contamination, Semiconducting wafers, Pellicles, Ultraviolet radiation, Ions, Scanners, Inspection, Chromatography

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Proceedings Article | 24 May 2004 Paper

Paper

Reticle surface contaminants and their relationship to sub-pellicle defect formation

Brian Grenon, Kaustuve Bhattacharyya, William Volk, Khoi Phan, Andre Poock

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536584

KEYWORDS: Reticles, Air contamination, Ions, Inspection, Quartz, Contamination, Raman spectroscopy, Pellicles, Chemical analysis, Photomasks

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Proceedings Article | 11 March 2002 Paper

Paper

ArF (193-nm) alternating aperture PSM quartz defect repair and printability for 100-nm node

Jerry Chen, John Riddick, Matt Lamantia, Azeddine Zerrade, Robert Henderson, Greg Hughes, Cyrus Tabery, Khoi Phan, Chris Spence, Amy Winder, William Stanton, Eugene Delarosa, John Maltabes, Cecilia Philbin, Lloyd Litt, Anthony Vacca, Scott Pomeroy

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458362

KEYWORDS: Quartz, Photomasks, Semiconducting wafers, Scanning electron microscopy, Etching, Atomic force microscopy, Ions, Reticles, Inspection, Critical dimension metrology

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Proceedings Article | 14 September 2001 Paper

Paper

Automatic defect severity scoring for 193-nm reticle defect inspection

Linard Karklin, Mark Altamirano, Lynn Cai, Khoi Phan, Chris Spence

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435716

KEYWORDS: Photomasks, Reticles, Lithography, Inspection, Optical proximity correction, Semiconducting wafers, Virtual reality, Resolution enhancement technologies, Decision support systems, Critical dimension metrology

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Proceedings Article | 5 September 2001 Paper

Paper

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring

Lynn Cai, Khoi Phan, Chris Spence, Linyong Pang, Kevin Chan

Proceedings Volume 4409, (2001) https://doi.org/10.1117/12.438388

KEYWORDS: Semiconducting wafers, Photomasks, Reticles, Virtual reality, Scanning electron microscopy, Decision support systems, Critical dimension metrology, Optical proximity correction, Inspection, Tolerancing

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Proceedings Article | 22 January 2001 Paper

Paper

Correlation of reticle defects detectability and repairs to ArF wafer printability for 0.13-um design rule with binary OPC/SB mask

Khoi Phan, Chris Spence, John Riddick, Jerry Chen, Matt Lamantia, Hugo Villa

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410693

KEYWORDS: Reticles, Semiconducting wafers, Photomasks, Inspection, Scanning electron microscopy, Optical proximity correction, Binary data, Printing, 193nm lithography, Defect detection

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Proceedings Article | 21 July 2000 Paper

Paper

Manufacturability of the ultrathin resist process

Christopher Pike, Scott Bell, Marina Plat, Paul King, Khanh Nguyen, Christopher Lyons, Harry Levinson, Khoi Phan, Uzodinma Okoroanyanwu

Proceedings Volume 3997, (2000) https://doi.org/10.1117/12.390068

KEYWORDS: Photoresist processing, Semiconducting wafers, Scanning electron microscopy, Lithography, Etching, Manufacturing, Silicon, Inspection, Transistors, Photoresist materials

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Proceedings Article | 2 June 2000 Paper

Paper

Single closed contact for 0.18-micron photolithography process

Cristina Cheung, Khoi Phan, Robert Chiu

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386531

KEYWORDS: Photomasks, Semiconducting wafers, Optical lithography, Defect detection, Photoresist processing, Inspection, Oxides, Deep ultraviolet, Failure analysis, Semiconductors

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With the rapid advances of deep submicron semiconductor technology, identifying defects is converted into a challenge for different modules in the fabrication of chips. Yield engineers often do bitmap on a memory circuit array (SRAM) to identify the failure bits. This is followed by a wafer stripback to look for visual defects at each deprocessed layer for feedback to the Fab. However, to identify the root cause of a problem, Fab engineers must be able to detect similar defects either on the product wafers in process or some short loop test wafers. In the photolithography process, we recognize that the detection of defects is becoming as important as satisfying the critical dimension (CD) of the device. For a multi-level metallization chemically mechanical polish backend process, it is very difficult to detect missing contacts or via at the masking steps due to metal grain roughness, film color variation and/or previous layer defects. Often, photolithography engineer must depend on Photo Cell Monitor (PCM) and short loop experiments for controlling baseline defects and improvement. In this paper, we discuss the findings on the Poly mask PCM and the Contact mask PCM. We present the comparison between the Poly mask and the Contact mask of the I-line Phase Shifted Via mask and DUV mask process for a 0.18 micron process technology. The correlation and the different type of defects between the Contact PCM and the Poly Mask are discussed. The Contact PCM was found to be more sensitive and correlated to contact failure at sort yield better. We also dedicate to study the root cause of a single closed contact hole in the Contact mask short loop experiment for a 0.18 micron process technology. A single closed contact defect was often caused by the developer process, such as bubbles in the line, resist residue left behind, and the rinse mechanism. We also found surfactant solution helps to improve the surface tension of the wafer for the developer process and this prevents/eliminates a single closed contact hole defects. The applications and effects of using different substrates like SiON, different thicknesses of Oxides, and Poly in the Contact Photo Mask is shown. Finally, some defect troubleshooting techniques and the root cause analysis are also discussed.

Proceedings Article | 2 June 2000 Paper

Paper

Defect printability for sub-0.18-micron design rules using 193-nm lithography process and binary OPC reticle

Khoi Phan, Chris Spence, Jeff Schefske, Uzodinma Okoroanyanwu, Harry Levinson

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386536

KEYWORDS: Reticles, Semiconducting wafers, Photomasks, Lithography, Scanning electron microscopy, 193nm lithography, Binary data, Optical proximity correction, Antimony, Scanners

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Proceedings Article | 30 December 1999 Paper

Paper

Comparison of binary mask defect printability analysis using virtual stepper system and aerial image microscope system

Khoi Phan, Chris Spence, S. Dakshina-Murthy, Vidya Bala, Alvina Williams, Steve Strener, Richard Eandi, Junling Li, Linard Karklin

Proceedings Volume 3873, (1999) https://doi.org/10.1117/12.373301

KEYWORDS: Photomasks, Semiconducting wafers, Reticles, Scanning electron microscopy, Inspection, Optical proximity correction, Binary data, Photoresist processing, Microscopes, Lithography

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Proceedings Article | 8 June 1998 Paper

Paper

Efficient and cost-effective photo defect monitoring

Khoi Phan, Robert Chiu, Shobhana Punjabi, Bhanwar Singh

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308785

KEYWORDS: Semiconducting wafers, Oxides, Wafer testing, Silicon, Photoresist processing, Defect detection, Particles, Inspection, Deep ultraviolet, Manufacturing

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Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects during the fabrication process. Defect densities are monitored on product wafers to determine whether the line maintains an acceptable yield level and to prevent any catastrophic downfall. However, defect detection is difficult for multilayer devices. A short loop defect monitor is often employed in the Photolithography area for inspection on an automated wafer inspection system like the KLA 213x. This monitor usually uses clean bare Silicon wafers which are processed through a Photocluster cell to define a resist pattern for defect inspection. In order to monitor a large set of equipment and resist types, a large quantity of clean Silicon wafers are required. The reuse of these silicon photo monitor wafers becomes difficult due to particles left on wafers after resist clean. Thus, the cost of daily photo defect monitor for equipment/process control becomes considerable. In this paper, we will discuss reusable thermal oxide test wafers as an alternative solution to Si wafers for a cost effective photo defect monitor. The required oxide thickness for I-line and DUV resists was calculated from Prolith/2 simulation. By using a special clean with Sulfuric Acid/Hydrogen Peroxide mixture (SPM) and followed by an Ammonium Hydroxide/Hydrogen Peroxide mixture (APM) for resist strip, very low particle counts were achieved for oxide substrate and better than those of Silicon wafers. Furthermore, due to low oxide thickness loss per clean cycle (1 - 2 A), oxide test wafers retain the optical characteristics for defect metrology tools to work without any recalibration. This makes the oxide photo defect monitor process very robust and production worthy. KLA defect data on unpatterned and patterned oxide test wafers for 20 or more reworks, will be shown. They will be compared to control Silicon test wafers. Some issues with exposure and focus condition and their effect on KLA defect detection will be discussed. Finally, a simple cost analysis model will show the potential saving benefit of oxide test wafer.

Proceedings Article | 8 June 1998 Paper

Paper

Methodology for the optimization of an i-line lithographic process for defect reduction

Khoi Phan, Gurjeet Bains, David Steele, Jonathan Orth, Ramkumar Subramanian

Proceedings Volume 3332, (1998) https://doi.org/10.1117/12.308739

KEYWORDS: Photoresist processing, Semiconducting wafers, Scanning electron microscopy, Lithography, Standards development, Inspection, Silicon, Etching, Photoresist developing, Metals

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As device geometries shrink into the sub-half micron regime, controlling and reducing defect levels becomes increasingly important in both R&D and Manufacturing environments. Any delay in addressing the causes and cures of these yield killers can prolong the development cycle and production release of new product technologies. However, defect evaluation for a new lithography process on product wafers is difficult due to metrology limitation, substrate noises and previous layer defects. This problem is particularly pronounced for backend layers where differences in the metal grain sizes and reflectivity can confound defect inspection tools and can be picked up as false defects. Often yield learning is long delayed awaiting sort data, before lithographers can determine the beneficial effects of proposed manufacturing improvements. In this paper, we will discuss a methodology for optimizing an I-line lithographic process with the aid of a photo defect monitor. Clean Silicon wafers were fully processed through a photocluster cell to simulate the actual processing conditions for the product, then inspected on a KLA 2132 for pattern defects. An in-line low voltage SEM system was used to review and to classify defect types. In a case study presented here, post develop residue was found to be the predominant defect for a new I-line resist used in the backend layers of the 0.25 micrometer process technology. The resolution of the resist residue deposition problem was commenced by evaluating different processes with multiple puddles/rinses for their defect densities. Based on this work, a low defect developer process was chosen for further study. Other process variables such as resist profile, CD uniformity and Etch bias as well as electrical defect parameters were compared between the old and the new processes. The goal is to demonstrate that given equal performance in all other respects, a quick implementation of this new low defect process, prior to the sort yield confirmation, would not have any detrimental effect on device yield. An example of a non- killer defect, water stain droplets, discovered during the defect review will be shown. Further refining of the dry cycle in the process eliminated this cosmetic defect. Finally, the KLA defect trend chart will show an improvement in defect density with the new develop process.

Proceedings Article | 7 July 1997 Paper

Paper

Novel approach for defect detection and reduction techniques for submicron lithography

Jonathan Orth, Khoi Phan, David Steele, Roger Young

Proceedings Volume 3050, (1997) https://doi.org/10.1117/12.275952

KEYWORDS: Photoresist processing, Optical lithography, Semiconducting wafers, Lithography, Scanning electron microscopy, Submicron lithography, Image processing, Metrology, Defect detection, Semiconductors

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Proceedings Article | 1 July 1991 Paper

Paper

Metrology issues associated with submicron linewidths

Khoi Phan, John Nistler, Bhanwar Singh

Proceedings Volume 1464, (1991) https://doi.org/10.1117/12.44455

KEYWORDS: Scanning electron microscopy, Calibration, Metrology, Integrated optics, Integrated circuits, Inspection, Process control, Critical dimension metrology, Optical testing, Photomasks

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Proceedings Article | 1 June 1990 Open Access

Open Access

Paper

0.5-um photolithography using high-numerical-aperture I-line wafer steppers

William Arnold, Anna Maria Minvielle, Khoi Phan, Bhanwar Singh, Michael Templeton

Proceedings Volume 1264, (1990) https://doi.org/10.1117/12.20184

KEYWORDS: Optical lithography, Semiconducting wafers, Lithography, Silicon, Chlorine, Monochromatic aberrations, Helium, Scanning electron microscopy, Printing, Deep ultraviolet

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Showing 5 of 17 publications

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