Electron beam (EB) metrology of Ge channel gate-all-around (GAA) FET (field effect transistor) was investigated. Ge-GAA FET is one of the promising candidates for high performance pMOS device of future node. Ge is superior to Si in hole mobility which can be enhanced further by applying compressive channel strain in GAA structure with SiGe strain relaxed buffer (SRB). Coincide with this advantage, channel buckling could happen more easily. Thus, a monitoring method of channel buckling is required. Chemical instability of Ge is another issue in fabrication process. It is suspected that EB irradiation during SEM inspection could cause the deterioration of device performance. On this background, following two evaluations were performed. The first one is quantitative evaluation of channel buckling. It is found that the channel buckling can be quantified with a proposed buckling index. The second one is assessment of the EB-induced damage on the electrical properties. The results showed that EB irradiation on Ge channels does not affect the device performance when the device is annealed adequately. In conclusion, EB metrology is effective for the evaluation of channel buckling and applicable to Ge channels without deterioration of the device performance.
KEYWORDS: Germanium, Gallium nitride, Gallium arsenide, CMOS technology, Field effect transistors, Fin field effect transistors, Group III-V semiconductors
With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.
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