Dr. Lieve Teugels Profile

Dr. Lieve Teugels

at imec

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Author

Publications (5)

Proceedings Article | 13 June 2022 Presentation

MOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)

Zheng Tao, Yisuo Li, Waikin Li, Minsoo Kim, Basoene Briggs, Katia Devriendt, Lieve Teugels, Farid Sebai, Christophe Lorant, Clement Porret, Erik Rosseel, Alfonso Sepúlveda Márquez, Nicolas Jourdan, Juergen Boemmels, Jerome Mitard, Philippe Matagne, Efrain Altamirano-Sánchez, Lars-ake Ragnarsson, Anish Dangol, Dmitry Batuk, Gerardo Tadeo Martinez Alanis, Jef Geypen, Kenichi Kanazawa, Testuo Izawa, Masakazu Kakumu, Koji Sakui, Nozomu Harada

Proceedings Volume PC12056, PC120560B (2022) https://doi.org/10.1117/12.2614772

KEYWORDS: Optical lithography, Metals, Etching, Transistors, Atomic layer deposition, Silica, Inspection, Electrodes, Transmission electron microscopy, System on a chip

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Proceedings Article | 25 May 2022 Presentation + Paper

Buried power rail integration for CMOS scaling beyond the 3 nm node

A. Gupta, Z. Tao, D. Radisic, H. Mertens, O. Varela Pedreira, S. Demuynck, J. Bömmels, K. Devriendt, N. Heylen, S. Wang, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, S. Subramanian, F. Schleicher, A. Peter, N. Rassoul, Y. Siew, B. Briggs, D. Zhou, E. Rosseel, E. Capogreco, G. Mannaert, A. Sepúlveda, E. Dupuy, K. Vandersmissen, B. Chehab, G. Murdoch, E. Altamirano Sanchez, S. Biesemans, Zs. Tőkei, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12056, 120560B (2022) https://doi.org/10.1117/12.2615641

KEYWORDS: Ruthenium, Metals, Molybdenum, Etching, Tungsten, Front end of line, Chemical mechanical planarization, Silicon

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Proceedings Article | 26 February 2021 Presentation + Paper

28nm pitch single exposure patterning readiness by metal oxide resist on 0.33NA EUV lithography

D. De Simone, L. Kljucar, P. Das, R. Blanc, C. Beral, J. Severi, N. Vandenbroeck, P. Foubert, A. Charley, A. Oak, D. Xu, W. Gillijns, J. Mitard, Z. Tokei, M. van der Veen, N. Heylen, L. Teugels, Q. T. Le, F. Schleicher, P. Leray, K. Ronse, Il Hwan Kim, Insung Kim, Changmin Park, Jisun Lee, Koungmin Ryu, P. De Schepper, J. Doise, M. Kocsis

Proceedings Volume 11609, 116090Q (2021) https://doi.org/10.1117/12.2584713

KEYWORDS: Extreme ultraviolet lithography, Optical lithography, Oxides, Metals, Extreme ultraviolet, Scanners, Scanning electron microscopy, Photoresist processing, Lithography, Line edge roughness

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For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.

Proceedings Article | 20 March 2019 Paper

Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies

N. Collaert, A. Alian, B. De Jaeger, U. Peralagu, A. Vais, A. Walke, L. Witters, H. Yu, E. Capogreco, K. Devriendt, T. Hopf, K. Kenis, G. Mannaert, A. Milenin, A. Peter, F. Sebaai, L. Teugels, D. van Dorp, K. Wostyn, N. Horiguchi, N. Waldron

Proceedings Volume 10963, 1096305 (2019) https://doi.org/10.1117/12.2511746

KEYWORDS: Germanium, Gallium nitride, Gallium arsenide, CMOS technology, Field effect transistors, Fin field effect transistors, Group III-V semiconductors

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Proceedings Article | 20 March 2019 Paper

Plasma etch selectivity study and material screening for self-aligned gate contact (SAGC)

Dunja Radisic, Marc Demand, Shihsheng Chang, Steven Demuynck, Kaushik Kumar, Andrew Metz, Lieve Teugels, Junling Sun, Jeffrey Smith, Farid Sebaai, Toby Hopf, Efrain Altamirano Sánchez

Proceedings Volume 10963, 109630P (2019) https://doi.org/10.1117/12.2505129

KEYWORDS: Etching, Silicon carbide, Plasma etching, Silicon, Plasma, Fluorine, Polymers, Dielectrics, Polymer thin films, Optical lithography

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Self-Aligned Gate Contact (SAGC) integration is design based on formation of the two separate contacts to the source/drain (S/D) and to the gate (G), which are realized in two separate plasma etch steps. Essentially, the first one is the contact plug (CP) etch over S/D contact selective to the gate plug (GP) and sidewall spacer (SWS), and the second one is the gate plug (GP) etch selective to the contact plug (CP) and the sidewall spacer (SWS). Therefore, the high selectivity plasma etch processing for the CP and GP towards the other two relevant, neighboring films is a key requirement for successful SAGC integration. In this paper we present plasma etch process development required for SAGC implementation, primarily focusing on the multi-color selectivity studies, i.e., selective CP (towards GP and SWS) as well as selective GP (towards CP and SWS) at contacted poly pitch (CPP) 42nm. The primary (‘standard’) integration scheme uses SiO₂ CP, Si₃N₄ GP and SiCO SWS. Furthermore, we investigate the “alternative’ integration scheme with SiCxNy films as replacement of the traditionally used SiO₂ CP material aiming to simplify the patterning sequence and ease high selectivity requirements. We report the selectivity values obtained on the CP/GP/SWS multi-color stack for the CP plasma processing (SiO₂ or SiC_xN_y) towards Si₃N₄ and SiCO; as well as for GP (Si₃N₄) plasma dry etch process towards SiO₂ or SiC_xN_y and SiCO. Using a Quasi-ALE (Q-ALE) approach for selective SiO₂ etch process is developed with a selectivity of 8 to 1 towards Si³N₄ and SiCO. For the selective Si₃N₄ etch continuous wave plasma CH₃F-based process is developed and selectivity of 9 to 1 towards SiO₂ and SiCO achieved. In the case of the integration scheme with SiC_xN_y CP, the selectivity for SiC_xN_y etch towards Si₃N₄ GP and SiCO SWS higher than 20 to 1 is accomplished using continuous RF source NF₃/O₂- based process. As for the Si₃N₄ plasma etch in the ‘alternative’ scheme using CH₃F/O₂-based process, the selectivity towards SiC_xN_y of higher than 20 to 1 and selectivity to SiCO of around 10 to 1 is achieved.

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