In this study we examine several innovations. In lithography, we introduce our latest progress on metal oxide resist (MOR) to extend defectivity window, improve photo-speed, and wafer uniformity control by leveraging new resist development techniques.
On the plasma etch front, we focus on plasma-resist interactions and the impact of the pattern transfer process. Gas chemistry and plasma characteristics can modulate resist rectification, leading to a widening of the defectivity window and smoothing of pattern roughness. Especially, when reducing line-space pattern defectivity, correlations between plasma characteristics and microbridge defect numbers point to a proper process regime for patterning in the sub 30nm pitch era.
In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.
We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes, the fabrication of multi-layer films requires the precision of atomic scale XY CD controllability in complex hole patterns. In order to solve the requirement, we have developed Advanced Quasi- Atomic Layer Etching (ALE) technology which achieved X-Y CD control in oval patterns, along with a wider X-Y CD control margin. Furthermore, in the memory fabrication process, it is required to vertically etch the organic film mask pattern in high aspect ratio (A/R) feature. Therefore, we have developed a new approach that combines atomic layer deposition (ALD) technique and organic film etch process. With this method, we are able to achieve the vertical mask profile. Thus, we will show that these new process technologies have a significant potential to solve critical challenges in the various processes in advanced nodes.
In patterning etch processes, the fabrication of multilayer films requires the precision of atomic scale X-Y CD controllability in complex hole patterns, and reduction of local variability such as Line Edge Roughness (LER), Line Width Roughness (LWR) and Local CDU (LCDU). In order to solve these requirements, we have developed Advanced Quasi-ALE technology which achieved reduction of LCDU, along with a wider X-Y CD control margin. In this paper, we introduce the three benefits of our atomic scale CD and variability control process technology; (1) XY CD control in oval patterns, (2) LCDU reduction and (3) wider etching window using Advanced Quasi-ALE technique. Hence, we will show that it has a significant potential to solve critical challenges in the patterning processes of N5 and beyond.
Research and development activities related to Extreme Ultra Violet [EUV] defined patterning continue to grow for < 40 nm pitch applications. The confluence of high cost and extreme process control challenges of Self-Aligned Quad Patterning [SAQP] with continued momentum for EUV ecosystem readiness could provide cost advantages in addition to improved intra-level overlay performance relative to multiple patterning approaches. However, Line Edge Roughness [LER] and Line Width Roughness [LWR] performance of EUV defined resist images are still far from meeting technology needs or ITRS spec performance. Furthermore, extreme resist height scaling to mitigate flop over exacerbates the plasma etch trade-offs related to traditional approaches of PR smoothing, descum implementation and maintaining 2D aspect ratios of short lines or elliptical contacts concurrent with ultra-high photo resist [PR] selectivity. In this paper we will discuss sources of LER/LWR, impact of material choice, integration, and innovative plasma process techniques and describe how TELTM VigusTM CCP Etchers can enhance PR selectivity, reduce LER/LWR, and maintain 2D aspect ratio of incoming patterns. Beyond traditional process approaches this paper will show the utility of: [1] DC Superposition in enhancing EUV resist hardening and selectivity, increasing resistance to stress induced PR line wiggle caused by CFx passivation, and mitigating organic planarizer wiggle; [2] Quasi Atomic Layer Etch [Q-ALE] for ARC open eliminating the tradeoffs between selectivity, CD, and shrink ratio control; and [3] ALD+Etch FUSION technology for feature independent CD shrink and LER reduction. Applicability of these concepts back transferred to 193i based lithography is also confirmed.
This paper introduces a new technique utilizing a direct current superimposed (DCS) capacitively-coupled plasma (CCP)
to enhance the etch selectivity to EUV resist with decreasing line width roughness (LWR). This new technique includes
chemical and e-beam curing effects. DCS CCP generates ballistic electrons, which reform the chemical structure of
photoresist. This surface modification hardens the photoresist (PR), and enhances the etch selectivity. The PR-hardening
technique also improves the tolerance towards stress by polymer. Hence, a polymer becomes applicable to protect
photoresist, and the etch selectivity increases even more. As a result, this cure can be processed without consuming the
thickness of EUV resist. The mechanism of EUV resist cure is discussed based on the surface analysis. In addition to the
basic physics of PR-hardening, this paper shows the benchmark results between DCS CCP and the conventional curing
techniques by RIE, such as HBr cure and H2 cure. Several new chemistries were applied to DCS CCP. In consequence,
the PR-hardening by DCS CCP achieved a 33% reduction in LWR at pre-etch treatment, and a 30% reduction during
under layer etch simultaneously maintaining enough thickness of EUV resist.
The root causes of issues in state-of-the-arts resist mask are low plasma tolerance in etch and resolution limit in
lithography. This paper introduces patterning enhancement techniques (PETs) by reactive ion etch (RIE) that solve the
above root causes. Plasma tolerance of resist is determined by the chemical structure of resin. We investigated a hybrid
direct current (DC) / radio frequency (RF) RIE to enhance the plasma tolerance with several gas chemistries. The DC/RF
hybrid RIE is a capacitive coupled plasma etcher with a superimposed DC voltage, which generates a ballistic electron
beam. We clarified the mechanism of resist modification, which resulted in higher plasma tolerance[1]. By applying an
appropriate gas to DC superimposed (DCS) plasma, etch resistance and line width roughness (LWR) of resist were
improved. On the other hand, RIE can patch resist mask. RIE does not only etch but also deposits polymer onto the
sidewall with sedimentary type gases. In order to put the deposition technique by RIE in practical use, it is very
important to select an appropriate gas chemistry, which can shrink CD and etch BARC. By applying this new technique,
we successfully fabricated a 35-nm hole pattern with a minimum CD variation.
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