KEYWORDS: Oxides, Transistors, Data modeling, Interfaces, Field effect transistors, Instrument modeling, Dielectrics, Signal to noise ratio, Electrons, Analog electronics
An analytical model for 1/f gate noise is developed and applied to the simulation and the characterization of ultra-thin
MOSFETs. The proposed model is based on oxide trapping mechanisms and uses the concept of equivalent flat band
voltage fluctuations. The developed model reproduces experimental behaviors. The power spectral density of flat band
voltage fluctuation extracted from gate current low frequency noise is compared to one extracted from drain low
frequency noise. Moreover, we have performed 1/f gate current noise for various drain voltage, and we show that there is
no impact of the drain current noise on the gate current noise. We also investigate RTS noise observed on the gate
leakage current. Finally, we present the characterization of the gate to drain overlap leakage current and its influence on
gate current noise level.
A characterization of low frequency noise in submicron N-MOSFETs is presented. For large devices, it is found that 1/f noise results from carrier number fluctuations. The slow oxide interface trap density deduced from noise data is found around 1016 eV-1 cm-3 in agreement with state-of-the-art gate oxides. Submicron devices present R.T.S noise and exhibit three independent active traps in saturation range, from weak to strong inversion. All of these traps have been found as acceptor type centers. Their activity ranges, their maximum of activities and their positions in the oxide from the Si-SiO2 interface have been obtained by the study of emission and capture times against gate voltage. It is shown existing overlap in trap activities for particular gate bias ranges. This overlap is confirmed by the observation of multi level R.T.S in time and frequency domains. For each trap, the number of R.T.S events is explained using the trap occupation probability. Finally, the global R.T.S behavior of devices, including the whole trap activities from weak to strong inversion, could be described using the simple R.T.S model classically used for a single oxide trap. This global study shows a simple method to determine R.T.S impact, and describes perfectly multi-trap activity.
An overview of the theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependence of 1/f noise in all conduction regime are summarized. Recent experimental studies on 1/f noise in MOS transistors are presented with special emphasis for PMOS from a 90 nm CMOS technology. Gate and drain noise sources are investigated. It is shown that in subthreshold regime drain current noise agrees with carrier number fluctuation model whereas in strong inversion the evolutions can be described by mobility fluctuation model. Gate current noise shows 1/f and white noise. White noise is very close to shot noise, and we have a quadratic variation of 1/f noise with gate current. Coherence measurements show that the increase of drain noise at high gate biases can be attributed to tunneling effects. Input-referred gate noise and the volume trap density can be used as figure of merit. Discrepancies with the ITRS roadmap are discussed.
Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE, HSPICE and recently BSIM3v3l. The aim of this paper is to show the limitation of each of these implementations by comparison between noise simulations and noise measured data. We demonstrated that 1/f noise model implemented in SPICE and HSPICE can not predict correctly noise in all operating regimes which limit their usefulness for design purposes. We show that BSIM3v3 allows the better fitting with experimental noise results in all operating regimes.
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