We have designed new THz metastructure waveguides on Si wafers, aimed for low propagation loss and integration with
Si-based integrated circuits. The waveguide has a round cross-sectional hollow-core, surrounded by high reflectioncladding-
walls formed by high-contrast metastructure gratings. We developed a new fabrication technique to fabricate
such a 3D metastructure cage waveguide structure. The waveguide is built using the entire wafer thickness which
involves deep Si etching of periodically spaced holes and using isotropic undercut etching to create a connecting a line
of etched spheres in the middle of the wafer to form the waveguide’s hollow core, then deep etch the high-contrast
grating through the entire wafer thickness to form the cladding for the waveguide. We have successfully modeled and
fabricated such a waveguide structure. The next step is to experimentally test and characterize the waveguide in the THz
spectrum range.
We have developed a new type of Si-based 3D cage-like high-contrast metastructure waveguide with both “slow-light”
and low-loss properties, which has applications in providing a long time-delay line or a high Q cavity in chip-scale optoelectronic integrated circuits (OEIC). Traditional semiconductor optical waveguides always have high loss when used in a high dispersion (slow-light) region. A preliminary computational model has predicted that there is a slow-light and low propagation loss region within cage-like hollow-core waveguide formed by 4 high-contrast-gratings walls/claddings. Using our new processing technique, we fabricated several such waveguides on a Si wafer with different core sizes/shapes and different HCGs for 1550 operation wavelength. We have conducted experimental waveguide delay test measurements using a short optical pulse which indicate that the group velocity of these metastructure waveguides are in the range of 20- 30% of the speed of the light. Using a waveguide “cut-back” method, we have experimentally determined the propagation loss of these waveguides are in the range of 2-5dB/cm. We are also developing this type of high-contrast metastructure hollow-core waveguide for different operating wavelength/frequency such as THz for different applications.
We present a new type of Si-based, metastructure, hollow-core waveguide that has highly desirable "slow-light" and
low-loss properties for providing time-delays or high-Q cavities in chip-scale integrated OE circuits. This waveguide has
high contrast grating (HCG) metastructures as the 4 claddings/walls of a squared hollow-core structure. We have
successfully fabricated this 3-D metastructure waveguide using a new nano-fabrication techniques including one selfaligned,
cycled, modified Bosch etch process. Our computational modeling indicates that there is a slow-light region
with very little propagation loss. We will report our preliminary experimental waveguide test results for propagation loss
and group velocity.
We have designed and developed a new, simplified 3-dimensional (3D) Photonic Crystal (PhC) fabrication
technique that can be used to fabricate a nanoscale 3D structure from the 2D surface of a Si (or SOI) wafer with a
single lithography and self-aligned etching sequence. This technique produces deep trenches with controlled width
variation along the vertical direction. Using an alternating sequence of Bosch etches, a combined cryogenic etching
and/or chemical etching process, allows the Bosch etched layers to maintain the width defined by the mask, while
the cryogenic/chemical etched layer creates a lateral undercut that decreases the width beneath the surface. The
result is a 3D lattice structure with a stack of vertical square grids. This paper reports the experimental procedures
and results of fabrication of a 3D lattice structure that forms an array of hollow-core waveguides. We also compare
several different etch recipes for the attempt to produce a uniform structure with smooth walls. These techniques
will reduce overall fabrication cost, increase yield and are compatible with CMOS processing. Using this method,
one can fabricate a variety of Si/SOI based 3D PhC structures including hollow-core, high contrast grating,
waveguide arrays.
We present the development of a fabrication technique for a semiconductor-based photonic crystal (PhC) nano-membrane device with reconfigurable active waveguides using micro-electro-mechanical systems (MEMS) technology. This device can be used as a basic building block for optoelectronic integrated circuits that can be reprogrammed for different functionalities such as switches, modulators, time delay lines, resonators, etc. The device is fabricated three-dimensionally on GaAs/Alx1GaAs/Alx2GaAs epitaxial layers on a GaAs substrate. The device has a top PhC membrane layer structure composed of hexagonal holes in a triangular lattice. Below that, a separate suspended bridge layer can insert a line of posts into the PhC holes to create a defect line. This MEMS feature can generate/cancel a section of the waveguide in the PhC platform, or (by partial removal) it can change the dispersion of the waveguide. Therefore, the same structure can be used as different types of devices. In this paper, we will discuss detailed fabrication processes for such a multi-layer 3D device structure, including e-beam lithography, inductively coupled plasma reactive ion etching, and multiple steps of regular photolithography and selective wet chemical etching. The unique processing sequence allows us to fabricate the multi-layer 3D device structure from one top surface without regrowth, wafer bonding, or access from the back surface. This simplifies the device processing and reduces the fabrication cost.
We present our design and fabrication of a semiconductor based photonic bandgap (PBG) nano-membrane device with MEMS features. This device could be used as a basic building block for a reconfigurable optoelectronic integrated circuit that can be reprogrammed for different functionalities. We combine a PBG platform with a MEMS feature to build such a reconfigurable device. The device has a top PBG membrane layer structure composed of hexagon holes in a triangular lattice. Below that, a separate suspended bridge layer can insert a line of posts into the photonic crystal holes to create a defect line. This MEMS feature can generate/cancel a section of the waveguide in the PBG platform, or it can change the dispersion of the waveguide. Therefore, the same structure can be used as different types of devices such as switches, modulators, time delay lines, etc. This device is fabricated on GaAs/Alx1GaAs/Alx2GaAs/GaAs-substrate epi-layers grown by MBE. We have developed the fabrication technique for such a device using e-beam lithography, inductively coupled plasma (ICP) reactive ion etching, and multiple steps of regular photolithography and selective wet chemical etching. The fabricated PBG membranes are 60 nm to 300 nm thick, with a thin wall between the holes of ~120 nm. A line of mushroom shaped MEMS posts are inserted into the ~1 μm PBG holes. We are fine tuning each of these processing steps toward the fabrication of a workable device.
We report on our design and fabrication of a semiconductor based photonic bandgap nano-membrane device with MEMS features. This device could be used as a basic building block for a reconfigurable optoelectronic integrated circuit that can be reprogrammed for many different functionalities.
A high-bandwidth, free-space integrated optoelectronic interconnect system was built for high-density, parallel data transmission and processing. Substrate-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) arrays and photodetector arrays, both driven by complimentary metal- oxide-semiconductor (CMOS) circuitry, were employed as a transmitter and receiver. We designed, fabricated, hybridized, and packaged the VCSEL transmitter and photoreceiver arrays. Data rates above 1 Gbs for each channel on the VCSEL/CMOS emitter and 500 MHz for each channel on photoreceiver were measured, respectively. We integrated the optical interconnects using free-space optical alignment and demonstrated serial and parallel transmissions of digital data and video images.
We report on the fabrication and characterization of interdigitated finger, optical detectors/mixers. These devices are used in an FM/cw ladar system to detect and demodulate low intensity amplitude-modulated optical signals. Three different types of interdigitated finger structure were tested and compared in this study. We also present a theory to explain the asymmetry observed in the devices and discuss its implication in an FM/cw ladar application.
A free-space integrated optoelectronic interconnect was built to explore parallel data transmission and processing. This interconnect comprises an 8 X 8 substrate-emitting 980-nm InGaAs/GaAs quantum-well vertical-cavity surface- emitting laser (VCSEL) array and an 8 X 8 InGaAs/InP P-I- N photodetector array. Both VCSEL and detector arrays were flip-chip bonded onto the complimentary metal-oxide- semiconductor (CMOS) circuitry, packaged in pin-grid array packages, and mounted on customized printed circuit boards. Individual data rates as high as 1.2 Gb/s on the VCSEL/CMOS transmitter array were measured. After the optical alignment, we carried out serial and parallel transmissions of digital data and live video scenes through this interconnect between two computers. Images captured by CCD camera were digitized to 8-bit data signals and transferred in serial bit-stream through multiple channels in this parallel VCSEL-detector optical interconnect. A data processing algorithm of edge detection was attempted during the data transfer. Final images were reconstructed back from optically transmitted and processed digital data. Although the transmitter and detector offered much higher data rates, we found that the overall image transfer rate was limited by the CMOS receiver circuits. A new design for the receiver circuitry was accomplished and submitted for fabrication.
The presentation gives an overview of the ongoing Army Research Laboratory (ARL)/University of Maryland research effort on vertical-cavity-surface-emitting-laser (VCSEL) interconnects and OE processing and why this technology is of interest. ARL is conducting a research and development effort to develop VCSELs, VCSEL arrays, and their hybridization with complimentary metal-oxide-semiconductor (CMOS) electronics and microwave monolithic integrated circuits (MMICs). ARL is also very active in the design, modeling, and development of diffractive optical elements (DOEs). VCSEL-CMOS flip-chip optoelectronic circuits and DOEs are of interest together with detector-CMOS flip-chip circuits to provide digital and analog optoelectronic interconnects in optoelectronic processing architectures. Such optoelectronic architectures show promise of relieving some of the information flow bottlenecks that are emerging in conventional digital electronic processing as the electronic state of the art advances at a rapid pace and the electronic interconnects become a significant limitation. Such optoelectronic interconnects are also of interest in the development of analog optoelectronic processing architectures that are very difficult to implement in conventional electronic circuitry due to the incorporation of dense arrays of interconnects between electronic elements. VCSEL-MMIC- detector flip-chip circuits are of interest for the incorporation of optoelectronic interconnects into analog RF systems where the optoelectronic interconnect offers advantages of size, weight, bandwidth, and power consumption. VCSEL-MMIC interconnects may also play a role in future high- speed digital optoelectronic processing.
KEYWORDS: Vertical cavity surface emitting lasers, Sensors, Photodetectors, Signal detection, Optoelectronics, Optical interconnects, Modulation, Signal attenuation, Detector arrays, Chemical elements
We demonstrate an optoelectronic interconnect based on an 8 by 8 array of vertical-cavity surface-emitting lasers, an 8 by 8 array of photodetectors, and a single compound lens. The substrate-emitting VCSEL array and back-illuminated photodetector array were flip-chip bonded to a CMOS driver circuit and a Si fan-out pad array, respectively. The CMOS driver provides laser addressing, signal conditioning and modulation current.In this paper we will describe the interconnect configuration, device structures and characteristics, and CMOS driver circuits. We then discuss the system operation and performance.
Erbium (Er) doped semiconductors are of interest for light- emitting device applications operating at around 1.55 micrometers and for the potential integration with other semiconductor devices. However, the optical emission of Er3+ ions in semiconductors has not been as efficient as in dielectric materials, particularly at room temperature. This may be because ionic bonds, which are characteristic of dielectrics, are better suited for forming the required Er3+ energy levels than are covalent bonds, which are present in most III-V semiconductors. In this paper, we report 1.55 micrometers emission from an Er-doped GaN LED. We also discuss effect of the measurement temperature on the emission spectrum as well as the effect of sample annealing on the emission spectrum.
We report a novel approach to normal incidence multiple quantum well light modulators. The quantum-confined Stark effect is utilized to tune the polarization rotation and phase retardation created by a thermally induced in-plane anisotropic strain. An exceedingly high contrast ratio of 4800:1 is demonstrated for a normally-on device at room temperature.
Lift-off thin films of GaAs/AlGaAs multiple quantum wells (MQW) have been bonded to different transparent substrates that possess either direction-independent or direction-dependent thermal expansion. Duet to the differential thermal expansion between the thin film and the much thicker substrate, the MQW is under a thermally induced in-plane strain. By proper choice of the substrate crystallographic orientation and bonding temperature various forms of in-plane anisotropic strain have been realized. A detailed study of the anisotropy in the complex refractive index resulting from the in-plane anisotropic strain is presented. The electric field dependence of the anisotropic absorption and birefringence has also been studied.
We present a systematic theoretical and experimental study on wavelength tuning and absorption lineshape of single bound state quantum well infrared photodetectors. We found that the absorption energy is determined by the energy level structure above the barriers as well as the shape of the quantum well ground state wave function. We calculated the absorption lineshape and show that it depends sensitively on the position of the final state relative to the global band structure of the detector. Using a quantum barrier as an electron energy high pass filter to discriminate against the lower energy dark current, we are able to increase the detectivity of the detector. The new device is referred as an IR hot-electron transistor. Its potential advantages in focal plane array applications will be discussed.
We report the observation of the excitonic recombination of degenerate quasi-two-dimensional electrons with localized photoexcited holes. Low-temperature photoluminescence spectra exhibit a sharp Fermi surface and a well resolved 'Mahan' exciton resonance which is sensitive to electron density ns and temperature. We observe a sharp decrease in the exciton linewidth with a concomitant double peak spectrum which is attributed to the formation of biexcitons and a large discontinuity in the exciton groundstate energy at ns approximately equals 1.9 X 1011 cm-2. An abrupt transition from excitonic to free electron-hole recombination occurs at ns approximately equals 2.2 X 1011 cm-2.
The Fermi level position in low temperature (LT) GaAs is studied by photoreflectance (PR). The experiments show that the Fermi level in both the as-grown and the annealed LT-GaAs is firmly pinned, however, the pinning position occurs at different energies: 0.47 eV below the conduction band edge for the as-grown samples and 0.65 eV below the conduction band edge for the annealed samples. The pinning in the as-grown LT-GaAs is the result of a high degree of charge compensation of deep levels, while the pinning in the annealed LT-GaAs is due to the depletion of carriers by the Schottky barrier at the metallic As precipitates. From the measured Fermi level and ionization ratio of As antisites, the (0/+) donor level of the As antisite is found to be at Ec - 0.57 eV.
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