Wafer-level nanoimprint lithography (NIL) has increasingly become a key enabling technology to support new devices and applications across a wide range of markets. Leading manufacturers of augmented reality (AR) devices, optical sensors and biomedical chips are already utilizing NIL and realizing the benefits of this technology, including the ability to mass manufacture micro- and nano-scale structures down with a maximum degree of freedom for the device dimensions. Another key advantage of this replication based technology is, given by the fact that even complex structures which require precise and time consuming fabrication methods can be transferred to mass manufacturing in an efficient semiconductor manufacturing line. Additionally, for many devices especially for optical applications the replicated layer can be directly used as functional layer in the product. Today NIL is considered as decisive process step for a number of emerging products, including AR waveguides. With increasing volumes the scaling of the production lines is crucial for most economical implementation of NIL. In particular for scaling to production lines using 200mm or even 300mm wafer sizes, the whole process chain has to be established. This is in particular a focus for AR devices requiring highly complex structures with tight specifications. Thus best efforts for master fabrication are crucial to obtain best performing devices. For smaller substrates, typically full area masters are used to manufactured and used for the NIL process. However, as the masters are mainly fabricated by sequential processes the costs scale with the pattern area. For 200mm and 300mm it has been proven to be viable option to start with single high-quality devices and scale them by step and repeat (SR) NIL to fully populated waferscale masters and subsequently to use those for volume manufacturing on wafer-level. The wafer-level production itself requires then reliable replication of working stamps and wafer level nanoimprinting of these multiple devices on a single wafer. As a result it is key for the high volume manufacturing to have a thorough understanding of all required pattering and replications steps to enable these large area manufacturing lines.
In this paper the rules-based correction strategies for the nanoimprint lithography (NIL) technology are addressed using complete Scanning Electron Microscopy (SEM) characterizations. Performed onto 200 mm wafers imprinted with the HERCULES NIL equipment platform, Critical Dimension (CD) uniformity analyses are used to measure the evolution of lines and spaces features dimensions from the master to 50 consecutive imprints. The work brings focus on sub micrometer resolution features with duty cycles from 3 to 7. The silicon masters were manufactured with 193 optical lithography and dry etching and were fully characterized prior to the imprint process. Repeatability tests were performed over 50 wafers for two different processes to collect statistical and comparative data. The data revealed that the CD evolutions can be modelled by quadratic functions with respect to the number of imprints and feature dimension (CD and pitch) on the master. These models are used to establish the rules-based corrections for lines arrays in the scope of nanoimprint master manufacturing, and it opens the discussion on the process monitoring through metrology for the nanoimprint soft stamp technologies.
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